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Farzad Mashayek is a Professor and Department Head of Aerospace and Mechanical Engineering at the University of Arizona, College of Engineering. He is a member of the Graduate Faculty and leads the Computational Multiphase Transport Laboratory. His research integrates high-fidelity simulations, machine learning, and experimental validation across diverse domains in fluid dynamics and energy systems. Educational Background: PhD in Mechanical Engineering, State University of New York at Buffalo, Buffalo, NY MS in Mechanical Engineering, Sharif University of Technology, Tehran, Iran BS in Mechanical Engineering, Sharif University of Technology, Tehran, Iran His research interests include turbulent reacting flows, plasma dynamics, electrostatic atomization, solid-ion and lithium batteries, computational fluid dynamics, and machine learning applications in engineering. He employs high-order spectral element methods, phase-field modeling, and deep neural networks to study complex multiphysics phenomena such as drop impact, battery degradation, and turbulence modeling. The recent publications reflect a strong trend toward integrating machine learning with multiphysics simulations, particularly in battery safety (thermal runaway prediction), materials characterization (STEM image analysis), and fluid dynamics (modal analysis of turbulence). His work often involves collaboration with experimental groups to validate models, especially in dental aerosol suppression and electrohydrodynamics. Scientific Awards: Sustained Service Award, American Institute of Aeronautics and Astronautics (AIAA), Spring 2022 Best Presentation Award, The 20th International Conference on Computational Mathematics, Parallel and Distributed Computing, Summer I 2018 Dr. Mashayek has secured funding from NSF (GOALI program) for controlled coating via charged droplet deposition. He advises graduate students and postdoctoral researchers in computational mechanics and energy systems, fostering interdisciplinary research. He has contributed to engineering education, particularly during the pandemic, with active learning strategies in online instruction. He leads a dynamic research team focused on advancing simulation tools and applying them to real-world challenges in energy, manufacturing, and public health.

• Turbulent Reacting Flow
• Plasma Flow
• Electrostatic Atomization
• +9 more

Sarita V Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign, where she conducts research spanning hardware, programming languages, operating systems, and applications with a focus on domain-specific systems. Her work bridges theoretical foundations and practical implementations, particularly in extended reality and heterogeneous computing. Her educational background includes a Ph.D. and M.S. in Computer Science from the University of Wisconsin-Madison (1993, 1989) and a B.Tech in Electrical Engineering from the Indian Institute of Technology Bombay (1987). Prior to joining Illinois, she served on the faculty at Rice University from 1993 to 1999. Adve's research centers on generalizable and scalable specialization for domain-specific systems, with current emphasis on extended reality (XR) systems including virtual, augmented, and mixed reality. She chairs the ILLIXR consortium to democratize XR research and developed the first fully open-source XR system (ILLIXR). Her foundational contributions include memory consistency models for C++ and Java programming languages, the Spandex coherence framework for heterogeneous systems, and software-driven approaches for hardware reliability. Her work spans hardware reliability (SWAT and RAMP projects), power management (GRACE system), and instruction-level parallelism. Recent publications reveal a strong focus on energy-efficient XR systems, hardware-software co-design for AI workloads, and resilience analysis. Her team explores rendering offload, visual-inertial odometry optimization, and compositional error injection frameworks, often targeting tradeoffs between energy, latency, and accuracy in mobile and edge environments. Fellow of the American Academy of Arts and Sciences Fellow of the ACM and IEEE ACM/IEEE-CS Ken Kennedy Award Anita Borg Institute Woman of Vision in Innovation Award ACM SIGARCH Maurice Wilkes Award Alfred P. Sloan Research Fellowship UIUC University Scholar University of Illinois Campus Award for Excellence in Graduate Student Mentoring Adve actively mentors students and has received multiple teaching awards. She co-founded the CARES movement to address discrimination in CS research events and chairs CS@Illinois CARES. Her service includes leadership roles in ACM SIGARCH (2015-2019), DARPA/ISAT study group, ACM Council, and Computing Research Association. She has secured significant funding including DARPA initiatives and Google Faculty Research Awards. She leads the ILLIXR consortium and has established collaborative research programs such as the $8.3M DARPA Joint University Microelectronics Program. Her lab focuses on open-source XR development, heterogeneous system architectures, and reliability-aware designs, with strong industry and government partnerships.

• Computer Architecture
• Extended Reality Systems
• Heterogeneous Computing
• +4 more

Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.

• Computer Architecture
• System-Level Design Automation
• Low Power Computing
• +3 more

Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.

• Reconfigurable Computing
• Field-Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• +3 more

Ozcan Ozturk is a Professor in the Computer Science and Engineering and Electronics Engineering programs at Sabancı University's Faculty of Engineering and Natural Sciences. Previously, he held professorships at Bilkent University and adjunct roles at North Carolina State University. His expertise spans heterogeneous computing, parallel systems, processor architecture, and compiler optimization. He earned his Ph.D. from Penn State University, with prior academic roles at the University of Florida and internships at Intel and Marvell. Education: Ph.D. in Computer Science and Engineering (2007), Pennsylvania State University M.S. in Computer Engineering (2002), University of Florida B.Sc. in Computer Engineering (2000), Bogazici University Research interests include accelerator technologies, GPU-based systems, multicore processors, and compiler optimizations. His work focuses on improving parallelization efficiency, energy optimization, and reliability in heterogeneous architectures. He leads funded projects like 'Machine Learning for Compiler Flags' and 'Graph Accelerator Design'. Notable awards include the Bilkent Teaching Award (2019), BAGEP (2018), and HiPEAC Paper Award (2016). He serves on editorial boards of IEEE and ACM journals and chairs major conferences like ASPLOS and ICS. Grants and collaborations include partnerships with Huawei, Intel, NVIDIA, and TÜBİTAK. He advises over 20 students and has supervised projects in safety-critical systems, FPGA accelerators, and compiler-directed optimizations. His lab develops domain-specific architectures, including RISC-V extensions for graph processing.

• Heterogeneous Computing
• Hardware Accelerators
• GPU Computing
• +7 more

Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.

• Field-programmable technology
• Electronic design automation (EDA)
• Hardware security
• +5 more

David I. August is a Professor of Computer Science at Princeton University, affiliated with the Department of Electrical Engineering. He earned his Ph.D. from the University of Illinois at Urbana-Champaign in 2000. His research focuses on compilers and computer architecture, emphasizing synergistic design between compilers and microarchitecture. He leads the Liberty Research Group, which explores topics such as automatic parallelization, memory profiling, and speculative execution. August joined Princeton in 1999 as a lecturer, advancing to full professor in 2012. He has served as program chair for MICRO 2009 and on committees for ISCA, PLDI, and ASPLOS. His notable accolades include the IEEE Fellow designation, Best Paper Awards at PLDI and CGO, and teaching awards from Princeton's School of Engineering. His work spans compiler optimizations, hardware-software co-design, and security architectures like TrustGuard. Recent research includes GPU scheduling (GhOST), memory profiling frameworks (PROMPT), and instruction prefetching (PDIP). He advises over 20 graduate students, many now leading roles at tech companies and academia. August teaches courses such as COS-126 (Intro to CS), COS-375 (Computer Architecture), and graduate seminars. His projects often bridge theory and practice, with tools like NOELLE and Liberty Research Group initiatives advancing compiler infrastructure and parallelism extraction.

• Compilers
• Computer Architecture
• Parallel Processing
• +4 more

Stephen W. Keckler is an Adjunct Professor at the Department of Computer Science , The University of Texas at Austin , and serves as Vice President of Architecture Research at NVIDIA . He is an ACM Fellow , IEEE Fellow , and Sloan Foundation Research Fellow . Education: BS in Electrical Engineering, Stanford University (1990) SM in Computer Science, Massachusetts Institute of Technology (1992) PhD in Computer Science, MIT (1998) Research Interests focus on computer architecture for deep learning , GPU computing , and energy-efficient systems . His work explores memory compression , network-on-chip designs , and heterogeneous computing . Publication Trends highlight advancements in deep learning accelerators , GPU memory systems , and energy-efficient architectures . Notable themes include sparsity exploitation , multi-chip modules , and fault-tolerant GPU pipelines . Scientific Recognition : ACM Fellow IEEE Fellow Sloan Foundation Research Fellow Best Paper Awards at ASPLOS 2009 and ISPASS 2011 Laboratory Affiliations : Computer Architecture and Technology Laboratory (CART) TRIPS Project (Tera-Op Reliable Intelligently adaptive Processing System) NVIDIA Research

• Computer Architecture
• Deep Learning Accelerators
• GPU Computing
• +4 more

Phillip B. Gibbons is a Professor in both the Computer Science Department and Electrical & Computer Engineering Department at Carnegie Mellon University. He received his Ph.D. in Computer Science from the University of California at Berkeley in 1989 and has held research positions at AT&T Bell Laboratories, Lucent Bell Laboratories, and Intel Research Pittsburgh before joining CMU's faculty. His research spans parallel computing, distributed systems, databases, computer architecture, and machine learning. Gibbons' work bridges theory and systems, with publications in top-tier conferences including SOSP, OSDI, SIGMOD, VLDB, NeurIPS, and many others across computer science and engineering disciplines. His research has been supported by significant funding from NSF, Intel, and other organizations. Gibbons has made substantial contributions to streaming algorithms, parallel computing frameworks, distributed systems security, and large-scale machine learning systems. His work on data stream algorithms with Alon, Matias, and Szegedy has been particularly influential in the field. He has served in numerous leadership roles including Editor-in-Chief of ACM Transactions on Parallel Computing (2012-2018) and on the editorial boards of Journal of the ACM and IEEE Transactions on Cloud Computing. He has also been active on program committees for major conferences in systems, databases, and theory. IEEE Fellow (2014) - For contributions to parallel computing and databases ACM Fellow (2006) - For contributions to parallel computing, databases, and sensor networks Selected for Oral Presentation at NeurIPS '13 (only 20 selected out of 1420 submissions) Co-winner of the best paper award for NSDI '06 Gibbons has advised numerous students and mentored researchers who have gone on to make significant contributions in academia and industry. His research has been supported by major grants including the $15M Intel Science and Technology Center for Cloud Computing (2011-2015) where he served as Co-PI/Co-Director. He currently leads research projects on write-efficient algorithms, big learning systems, and visual cloud systems. His laboratory work focuses on bridging theoretical computer science with practical systems implementation, particularly in the areas of parallel and distributed computing. Current research directions include adapting algorithms for emerging memory technologies and optimizing machine learning systems for large-scale deployment.

• Parallel Computing
• Distributed Systems
• Databases
• +4 more

Ana Maria Alonso Rodriguez is a Full Professor of Numerical Analysis at the Department of Mathematics, University of Trento. She holds a PhD in Applied Mathematics from Universidad Complutense de Madrid (1993) and has held academic positions across Italy and Spain since 1990. Her research focuses on numerical methods for partial differential equations, computational electromagnetism, finite element methods, and domain decomposition techniques. She has organized international workshops and minisymposia, including the 2022 Oberwolfach workshop on Hilbert Complexes and the 2018 ICOSAHOM conference session on high-order methods. Her work bridges numerical analysis, topology, and applied electromagnetism, with recent contributions to Whitney finite elements and discrete potential theory. Education: PhD in Applied Mathematics, Universidad Complutense de Madrid (1988-1993) Licenciatura en Ciencias Matematicas, same institution (1982-1987) Research emphasizes high-order discretizations for electromagnetic problems, leveraging finite element exterior calculus and graph-based decomposition techniques. Recent work (2024) advances tree-cotree methods for curl operator spectra and Whitney form interpolation. She actively collaborates with international institutions like the CI2MA in Chile and the Laboratoire J. A. Dieudonné in France. Teaching includes courses on numerical PDEs, finite elements, computational electromagnetism, and MATLAB-based numerical analysis at both undergraduate and PhD levels. She has supervised numerous courses in Italy and Spain since 2000, integrating practical software tools like FreeFem and MODULEF into instruction.

• Numerical Analysis
• Computational Electromagnetism
• Finite Element Methods
• +3 more

Alastair F. Donaldson is a Professor and Director of Research in the Department of Computing at Imperial College London, where he leads the FastPL research group. His work bridges formal methods, software testing, and programming languages, with a focus on enhancing the reliability of high-performance and parallel software systems. He has held key roles including Director of Research (since 2023) and previously served as Lecturer (2011–2014), Senior Lecturer (2014–2017), and Reader (2017–2020) before being promoted to Professor in 2020. His research interests include formal verification, compiler testing, GPU programming, concurrency, and fuzzing. He has made significant contributions to the verification of GPU kernels, metamorphic testing of graphics drivers, and the development of tools like GPUVerify and GraphicsFuzz. His work combines theoretical rigor with practical impact, demonstrated by the acquisition of his startup GraphicsFuzz by Google in 2018 and his subsequent roles as Senior Software Engineer and Visiting Researcher at Google. His recent publications reflect a sustained focus on compiler and system reliability, with trends in fuzzing, formal specification, and automated testing of complex systems such as WebGPU, CXL cache coherence, and large language models for code generation. His work increasingly integrates empirical validation with formal techniques to uncover subtle bugs in real-world systems. Scientific awards and recognitions include: 2017 BCS Roger Needham Award EPSRC Early Career Fellowship Fellow of the British Computer Society Best Paper awards at EuroSys 2024, MET 2021, IISWC 2019, IWOCL 2019, and ICST 2016 Best Industry Paper at ICST 2024 ACM SIGSOFT Distinguished Paper at ISSTA 2023 ACM SIGPLAN Most Influential OOPSLA Paper Award (2012 paper), awarded in 2022 Best Student Paper at PPoPP 2014 He has advised numerous PhD students and leads a vibrant research group. He has secured significant research funding and collaborates extensively with industry and academia. His service includes leadership roles such as General Chair of PLDI 2020, PC Chair of ECOOP 2019, and Steering Committee Chair of PLDI (2022–2025). He also serves on the advisory board of PACM-PL and on program committees for top venues including POPL, OOPSLA, PLDI, ICSE, and ISSTA. He leads the FastPL research group, which focuses on the design and implementation of programming tools and techniques for reliable software. The group conducts cutting-edge research in compiler testing, formal methods, and high-performance systems, fostering collaboration across academia and industry.

• Formal Verification
• Software Testing
• Programming Languages
• +12 more

Sharad Malik is the George Van Ness Lothrop Professor of Engineering at Princeton University's Department of Electrical and Computer Engineering. His research focuses on designing functionally correct and secure computing systems, combining system design with mathematical modeling for verification. He pioneered the Instruction-Level Abstraction (ILA) model for SoC verification and has contributed extensively to Boolean satisfiability (SAT) solvers. Education: PhD (1990), M.S. (1987) in Computer Science from UC Berkeley; B.Tech. (1985) in Electrical Engineering from IIT Delhi. Research Interests: Formal Verification of Digital Systems Hardware Security and Trust Boolean Satisfiability Solvers System-on-Chip (SoC) Design Accelerator-rich Platform Architectures Notable Achievements: IEEE CEDA A. Richard Newton Technical Impact Award (2017) 2013 IEEE/ACM DAC Most Cited Paper Award Princeton President’s Distinguished Teaching Award (2009) Advising & Labs: Leads the Malik Group, advising over 50 graduate students and postdocs. Active in postdoc recruitment and mentorship programs.

• Computer Science
• Hardware Security
• Digital Systems Design
• +5 more

Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.

• Computer Architecture
• Embedded Systems
• Real-Time Systems
• +3 more

Timothy M. Jones is a Professor of Computer Architecture and Compilation at the University of Cambridge Computer Laboratory, where he leads research in systems-level computing. He is also a Fellow at Gonville and Caius College, contributing to academic leadership and student mentorship within the collegiate system. His primary affiliation with the Computer Laboratory positions him at the forefront of systems research within the university. Dr. Jones's research focuses on extracting various forms of parallelism (thread-level, data-level, memory-level) to enhance computational performance while addressing energy efficiency and reliability challenges. His work spans compiler design, binary translation, and microarchitecture optimization, with specific interest areas including: Compiler technologies for functional and parallel programming Hardware reliability and fault tolerance mechanisms Binary analysis and instrumentation frameworks Memory system optimization and virtual memory management Security enhancements through binary modification Runtime systems for heterogeneous architectures Analysis of his recent publications reveals strong emphasis on systems-level innovation, particularly in fault tolerance techniques, binary analysis tools, memory optimization, and parallel execution frameworks. His work consistently bridges theoretical computer science with practical hardware implementation challenges. Dr. Jones maintains active participation in the academic community through conference leadership roles, including serving as Program Co-Chair for CGO 2026 and committee positions at premier venues including ISMM, CGO, and ECOOP. He contributes to open-source academic resources through GitHub and maintains professional engagement via Twitter.

• Compilers
• Computer Architecture
• Binary Modification
• +3 more

Yu Meng is an Assistant Professor in the Department of Computer Science at the University of Virginia (UVA), part of the School of Engineering and Applied Science. He joined UVA in 2024 as a tenure-track faculty member. His research focuses on machine learning, natural language processing (NLP), and data mining, with recent emphasis on large language models (LLMs), alignment, reliability, and ethical AI development. Educated at the University of Illinois Urbana-Champaign (UIUC), Meng earned his Ph.D. in 2023 under advisor Jiawei Han. His doctoral thesis, Efficient and Effective Learning of Text Representations , received the ACM SIGKDD 2024 Dissertation Award. He also held a visiting researcher position at Princeton University under Danqi Chen and was a Google PhD Fellow. His work has been recognized with awards including the Superalignment Fast Grant from OpenAI and notable publications at venues like NeurIPS, ICLR, and ACL. Meng’s research explores topics such as preference optimization (SimPO), retrieval-augmented generation (InstructRAG), and zero-shot learning. He actively serves on program committees for top conferences (ICLR, ICML, NeurIPS) and as an action editor for Transactions of Machine Learning Research (TMLR) . He teaches graduate-level courses on NLP, emphasizing cutting-edge LLM topics like architecture design, instruction tuning, and ethical considerations. Key achievements include contributions to LLM alignment via retrieval optimization, efficient pretraining techniques, and foundational work on weakly supervised learning. His research bridges theory and practice, addressing both technical challenges and societal impacts of AI systems.

• Machine Learning
• Natural Language Processing
• Data Mining
• +3 more