George Kesidis is a Professor in Computer Science and Engineering and Electrical Engineering at Penn State University. His research spans deep learning security, virtual reality optimization, and cloud computing. College of Engineering (Penn State University) Research Focus: Backdoor Attacks, DNN Robustness, Edge Caching Active in NSF and U.S. Navy-funded projects (2022-2026) His work addresses backdoor data poisoning , test-time evasion attacks , and DNN overfitting mitigation . He develops techniques like activation clipping, perturbation analysis, and statistical defense models. Recent projects include edge caching systems for VR and security-driven AI frameworks. Key article trends reveal expertise in adversarial deep learning, immersive media delivery, and cloud resource optimization. Current grants focus on multi-user VR, GPU scheduling, and serverless-cloud hybrid architectures. He collaborates extensively with researchers like David J. Miller and Xinyu Li, particularly on cloud-based adversarial defense mechanisms and VR streaming benchmarks.
Timothy M. Jones is a Professor of Computer Architecture and Compilation at the University of Cambridge's Computer Laboratory, serving as Director of the Computer Architecture and Semiconductor Design Centre (CASCADE) and Fellow/Director of Studies at Gonville and Caius College. His research focuses on parallelism extraction in applications to enhance performance and address energy efficiency/reliability challenges in compilers, binary translators, and microarchitectures. Current work includes novel cache prefetching techniques, thread-level parallelism schemes, and advanced core prediction methods. He has an Erdős number of 4 and a Dijkstra number of 4 via collaborative networks. Research interests span computer architecture fundamentals, compiler optimizations, hardware security mechanisms, and fault tolerance strategies. Notable contributions include speculative vectorization, heterogeneous parallel error detection (MEEK/FireGuard), and security tools like MarkUs and MineSweeper. CASCADE oversees interdisciplinary projects addressing future microprocessor/system challenges. Jones supervises PhD students through CASCADE's 2025 intake program. Publications emphasize architectural innovations in memory systems, security, and energy efficiency. Key works include MASCOT (memory dependence prediction), Scalar Vector Runahead (2024), and Decoupled Vector Runahead (2023). His work integrates hardware-software co-design principles to tackle real-world processor bottlenecks.
Zoran Budimlić is an Instructional Associate Professor in the Department of Computer Science and Engineering at Texas A&M University. He also serves as Director of Undergraduate Studies for Galveston. His roles include teaching and academic leadership in computer science education and high-performance computing. He holds a Ph.D. in Computer Science from Rice University (2001) and a B.S. in Computer Science and Engineering from the University of Belgrade (1994). His research interests focus on high-performance and parallel computing, compiler optimizations, programming languages, runtime systems, and high-level programming models. He emphasizes improving educational practices in computer science through innovative methods and curricula. His recent publications span parallel algorithms, task parallelism integration with MPI, and compiler optimizations for performance. Earlier work includes contributions to Java runtime optimization and static analysis techniques. Zoran Budimlić has no explicitly listed scientific awards or grants in the provided text, but his contributions to parallel computing and compiler design are notable. He advises students in these areas but no names are provided in the text.
Yihan Sun is an Assistant Professor at the University of California, Riverside (UCR) since January 2020. He earned his Ph.D. in Computer Science from Carnegie Mellon University (CMU) , advised by Guy Blelloch , and holds a Bachelor's degree in Computer Science from Tsinghua University . Research Interests: Yihan Sun focuses on the theory and practice of parallel computing , including Parallel algorithms and data structures Write-efficient algorithms for Non-Volatile Memory (NVM) Computational geometry (range trees, Delaunay triangulations) Graph algorithms (SSSP, SCC, cluster-based BFS) Concurrent and persistent data structures Multi-version concurrency control (MVCC) with garbage collection Applications in databases, transactional systems, and computational biology Recent Research Trends: His work on join-based parallel balanced trees has been foundational, supporting four balancing schemes (AVL, red-black, weight-balanced, treaps) and enabling efficient implementations in graph analytics, spatial queries, and dynamic programming. Recent publications focus on output-sensitive algorithms , scalable graph libraries (PASGAL) , and pedagogical approaches to teaching parallel algorithms. Teaching: He teaches CS260 (Parallel Algorithms) at UCR and has served as a guest lecturer for MIT 6.886 (Algorithm Engineering) and CMU 15-859 (Algorithms in the real world) . He also contributed to algorithm education through a tutorial at the ACM Symposium on Principles and Practice of Parallel Programming (PPoPP 2019) . Labs & Collaborations: Yihan is a core contributor to the PAM (Parallel Augmented Maps) library, which has been integrated into systems like Aspen (graph-streaming) and C-trees . He collaborates with teams at CMU-Parlay , PBBS , and Ligra , with his code available on Github for community feedback.
Thomas Yeh is an Assistant Professor of Teaching in the Department of Computer Science at the University of California, Irvine. His academic background includes a Ph.D. in Computer Science from UCLA and a BS in Electrical Engineering and Computer Science from UC Berkeley. Prior to academia, he gained industry experience across research, architecture, design, verification, marketing, and management roles. His educational credentials: Ph.D. in Computer Science, UCLA BS in Electrical Engineering and Computer Science, UC Berkeley Dr. Yeh's research spans computer architecture, accelerated machine learning, and computer science education. In architecture, he pioneers error-tolerant physics simulation and heterogeneous computing. His ML work focuses on adaptive precision techniques for energy-efficient acceleration. In education, he develops interactive tools for novice programmers and experiential learning frameworks for computer architecture. His cross-disciplinary approach bridges hardware-software co-design with pedagogical innovation. Publication trends reveal consistent focus on computational efficiency across physics simulation, ML acceleration, and educational technology. His work connects real-time systems optimization with emerging AI applications, particularly in interactive environments and physics-based animation. No scientific awards are documented in the provided materials. While advising details and grant funding specifics are absent from available information, his industry-academia transition informs practical research directions. Teaching responsibilities include core courses like Introduction to CS, Data Structures, and Efficient ML Computing. Research infrastructure details remain unspecified, though his publications suggest collaborations in physics simulation and heterogeneous computing environments.
Scott Mahlke is a Professor and Associate Chair in the Electrical Engineering and Computer Science Department at the University of Michigan. He is affiliated with the Advanced Computer Architecture Laboratory and the Software Systems Laboratory, where he leads the Compilers Creating Custom Processors (CCCP) research group. His research focuses on compilers, computer architecture, and high-level synthesis, with particular emphasis on designing next-generation computer systems that overcome challenges in performance, power consumption, and reliability. His work bridges the gap between hardware and software through innovative compiler technology that enables customized processors and accelerators. Mahlke's publications demonstrate a strong focus on compiler techniques for exploiting instruction-level parallelism, memory system optimization, and application-specific processor design. His research spans from fundamental compiler algorithms to practical implementations in both general-purpose and embedded systems. National Science Foundation CAREER Award (2003) Morris Wellman Faculty Development Assistant Professor (2004) 2006 ISCA Most Influential Paper Award Multiple best paper awards at major architecture conferences As an advisor, Mahlke has chaired numerous Ph.D. dissertations and actively mentors graduate students in the CCCP group. His research is generously funded by the National Science Foundation, Gigascale Systems Research Center, ARM Ltd., Samsung Advanced Institute of Technology, and other major organizations. The CCCP group maintains strong industry partnerships that facilitate the transfer of research innovations to practical applications.
Professor Saman Amarasinghe is a full Professor in the Department of Electrical Engineering and Computer Science (EECS) at the Massachusetts Institute of Technology (MIT), and Principal Investigator at MIT's Computer Science and Artificial Intelligence Laboratory (CSAIL). He leads the Commit compiler research group, which focuses on programming languages and compilers that maximize application performance on modern computing platforms. His work spans multiple academic departments and research centers, with strong affiliations to both MIT's School of Engineering and CSAIL. Professor Amarasinghe's research interests center around high-performance domain-specific languages and compiler technology . His work combines language design with sophisticated compilation techniques to deliver unprecedented performance for targeted application domains. His research spans multiple areas including image processing (Halide), sparse tensor algebra (TACO), graph analytics (GraphIt), stream computations (StreamIt), and bioinformatics (Seq). A significant thread throughout his work is the application of machine learning for compiler optimizations, from Meta optimization in 2003 to the OpenTuner autotuner framework. Analysis of Professor Amarasinghe's recent publications reveals a strong focus on sparse computing , compiler vectorization , and domain-specific language implementation . His work consistently bridges theoretical compiler concepts with practical performance gains across diverse application domains. The progression from earlier work on StreamIt and Halide to more recent projects like GraphIt and TACO shows an evolution toward more specialized, high-performance DSLs targeting specific computational patterns. His 2020-2025 publications particularly emphasize sparse tensor operations, GPU acceleration, and machine learning integration with compiler technology. ACM Fellow (2019) Professor Amarasinghe has made significant contributions to academic entrepreneurship and student development. He founded Determina, Inc. (acquired by VMware) based on security research from his MIT lab and co-founded Lanka Internet Services, Ltd., Sri Lanka's first ISP. As faculty director of MIT Global Startup Labs, his programs across 17 countries have helped create over 20 successful startups. His teaching includes the popular Performance Engineering of Software Systems (6.172) course with Professor Charles Leiserson, as well as innovative project-based courses like the Open Source Software Project Lab and Bring Your Own Software Project Lab. His educational approach emphasizes hands-on experience with compiler and language design concepts. Professor Amarasinghe leads the Commit compiler research group at MIT CSAIL, which has produced numerous influential domain-specific languages and compilers including Halide, TACO, Simit, StreamIt, and GraphIt. The lab maintains strong industry connections through projects like OpenTuner and Determina, and collaborates with researchers worldwide on compiler technology. The group's work spans both theoretical compiler research and practical implementation, with a consistent focus on bridging the performance gap between high-level programming abstractions and hardware capabilities.
Professor Ahmed Hemani is a faculty member at the Division of Electronics and Embedded Systems, KTH Royal Institute of Technology, affiliated with the Digital Futures Faculty. He holds the role of PI for the project 'New Chip Architectures for Industrial Vision' and leads research in reconfigurable computing, memristor-based systems, and hardware acceleration for AI and edge computing. His work bridges theoretical computer science with practical VLSI design and embedded systems development. He actively contributes to cross-disciplinary initiatives at Digital Futures, a joint center with Stockholm University and RISE Research Institutes of Sweden focused on digital innovation. His research emphasizes scalable FPGA/HPC architectures, low-power neuromorphic systems, and optimization techniques for custom silicon solutions. Current projects include a Lego-inspired edge AI framework and memristor-driven MIMO acceleration. Teaching responsibilities span advanced courses in SOC design, digital system verification, and embedded systems. He supervises advanced-level degree projects across computer engineering and ICT innovation specializations, emphasizing hands-on hardware-software co-design methodologies. Recent publications highlight innovations in memristor applications, FPGA-based acceleration, and reconfigurable architectures for neural networks and bioinformatics. His work addresses challenges in dark silicon utilization, energy-efficient computation, and high-performance embedded systems.
Prof. Dr. Dr. h.c. Gudrun Kiesmüller serves as Full Professor holding the Chair for Operations Management at TUM School of Management, Technical University of Munich, based at Campus Heilbronn since July 2019. She concurrently holds the position of Hedda Andersson Guest Professor at Lund University's Department of Industrial Management & Logistics since January 2021. Previously, she held professorial positions at Otto-von-Guericke-University Magdeburg (2013-2019), Christian-Albrechts-University zu Kiel (2010-2013), and Technical University Eindhoven (2002-2009). Her research program focuses on Operations Management with particular emphasis on the implications of digitization in Industry 4.0, especially in after-sales services. She develops analytical methods to optimize processes across manufacturing and supply chains. Her work spans three interconnected domains: stochastic manufacturing systems design (examining buffer sizing and spare parts planning), safety stock optimization under uncertain demand and supply conditions, and maintenance-reliability integration. She investigates how digitization transforms traditional operations, with growing emphasis on AI applications for supply chain optimization and inventory planning. Prof. Kiesmüller's extensive publication record reveals consistent contributions to operations research methodology with practical business applications. Her work demonstrates increasing integration of data-driven approaches, particularly in the most recent publications which explore AI applications for supply chain optimization. The research shows progression from theoretical inventory models toward more complex, integrated systems that consider multiple uncertainties simultaneously, reflecting the growing complexity of modern supply chains. Her professional recognition includes: 2022 Service Award from the International Society for Inventory Research Multiple Outstanding Reviewer Awards from OR Spectrum (2017, 2020) EURO Best Paper Award (2014) for influential review on lateral transshipments Multiple teaching awards recognizing excellence in both bachelor and master level instruction At TUM, Prof. Kiesmüller teaches a comprehensive curriculum in Operations Management, emphasizing both theoretical foundations and practical applications. Her courses equip students with skills to analyze supply chain planning problems, apply quantitative models, and solve complex operational challenges. She maintains an active research group investigating how digitization transforms operations management practices, particularly in after-sales service contexts where Industry 4.0 technologies enable new optimization possibilities.
Mateo Valero Cortés is a renowned Professor of Computer Architecture at the Polytechnic University of Catalonia and Director of the Barcelona Supercomputing Center (BSC). He has held academic and leadership roles since 1974, advancing high-performance computing (HPC) and computer architecture research. His work includes pioneering contributions to vector architectures, multithreading, and instruction-level parallelism. Education includes a Telecommunications Engineering degree from the Polytechnic University of Madrid (1974) and a PhD in Telecommunications Engineering from the Polytechnic University of Catalonia (1980). His research spans over 700 publications, focusing on HPC systems, parallel computing, and supercomputing infrastructure. Key research interests include vector processing, super-scalar processors, and task-based programming models. Recent work emphasizes scalable architectures for exascale computing and energy-efficient hardware-software co-design. Notable achievements include the Eckert-Mauchly Prize (highest in computer architecture), Seymour Cray Award, and Charles Babbage Prize. He has led initiatives like the Spanish Supercomputing Network (RES) and PRACE (European HPC partnership). Academic affiliations include the Royal Academy of Engineering of Spain, ACM Fellow, and IEEE Fellow. He has received 13 honorary doctorates and awards such as Mexico’s Order of the Aztec Eagle. Current projects include the Mont-Blanc HPC prototype and ERC-funded research on multi-core chip design. His BSC oversees over 300 researchers and manages MareNostrum supercomputers.
Berk Sunar is a Professor of Electrical & Computer Engineering and the founder of the Vernam Applied Cryptography and Cybersecurity Laboratory at Worcester Polytechnic Institute (WPI). He joined WPI in 2000 after holding postdoctoral and research roles at Oregon State University (OSU) and Trust Inc. His work focuses on applied cryptography, microarchitectural security, AI security, post-quantum cryptography, and homomorphic encryption. Sunar received his BSc from Middle East Technical University (1995) and PhD from Oregon State University (1998). Research interests include vulnerabilities in hardware (e.g., Rowhammer, TPM-FAIL), side-channel attacks, and cryptographic implementations. Notable contributions include discovering flaws in Intel CPUs and TPM chips affecting billions of devices, as well as developing defenses like cuHE (GPU-accelerated homomorphic encryption). Publications highlight breakthroughs in transient execution attacks (e.g., LVI, RIDL), post-quantum signature schemes (Dilithium), and cloud security (Firecracker VMM vulnerabilities). Awards include NSF CAREER (2002) and IBM Pat Goldberg Best Paper (2007). Advised over 30 graduate students, many of whom hold senior roles in academia and industry. Current research addresses AI security, quantum-resistant algorithms, and automated attack detection via machine learning. The Vernam Lab remains a hub for cybersecurity innovation.
Prof. Dr. rer. nat. Rainer Leupers is a faculty member at RWTH Aachen University, chairing the Department of Software for Systems on Silicon. His research focuses on embedded systems, hardware-software co-design, virtual prototyping, and security in computing-in-memory architectures. He has published extensively on RRAM accelerators, logic locking, and neuromorphic security. Chair of Software for Systems on Silicon Research in hardware security and deep learning accelerators Recent publications on cross-tool virtual frameworks and thermal side-channel attacks His work bridges system-level modeling with practical security implementations, emphasizing reliability and performance in heterogeneous computing environments. Key trends in his 2025-2023 articles include compute-in-memory optimization, neural network inference efficiency, and security vulnerabilities in emerging hardware. Awards and formal recognitions are not explicitly detailed in the provided materials. He has not directly mentioned advising students or research grants in the given text fragments. The chair's contact information includes an office at ICT Cube 1, Electrical Engineering, Aachen, with direct email and website links.
Luca Sterpone is a Full Professor at the Department of Control and Computer Science (DAUIN), Politecnico di Torino. He serves as Head of the Control and Computer Engineering Department (2023-2027), coordinates the Aerospace and Safety Computing Lab, and is a member of the Academic Senate and Power Electronics Innovation Center (PEIC). His research spans reconfigurable computing, fault tolerance, and radiation effects analysis in electronic systems. Professor since 2021 Department Head (DAUIN) since 2023 Coordinates international collaborations with ESA, AMD Xilinx, NVIDIA, and Thales Alenia Space Develops radiation-hardened FPGA tools (SETA, VERI-Place, PyXEL) 2007 EDAA Outstanding Dissertation Award and 2005 IEEE Best Paper Award Research Focus : Designing radiation-tolerant systems for aerospace, including fault-tolerant AI accelerators, FPGA reliability, and software-based error mitigation. He investigates soft error propagation in nanoscale circuits and develops tools for radiation sensitivity analysis in VLSI. His work integrates hardware-software co-design for mission-critical applications. Awards : EDAA Outstanding Dissertation Award (2007) IEEE European Test Symposium Best Paper (2005) SMACD Best EDA Tool Award (2018) ARC Best Paper candidate (2018) Teaching : He leads courses in Reconfigurable Computing (PhD level), GPU Programming , and Operating Systems . He has formal responsibility for teaching roles across 9 bachelor's and 7 master's years, and mentors multiple PhD students. Collaborations : Coordinates with the European Space Agency (ESA), University of Bielefeld, Universidad de Sevilla, and industrial partners like AMD Xilinx, NVIDIA, and General Motors. He leads projects such as RESCHIP4EU, VEGAS, and TERRAC for radiation-hardened computing solutions.
Sonia Lopez Alarcon is an Associate Professor in the Department of Computer Engineering at the Kate Gleason College of Engineering, Rochester Institute of Technology (RIT). She has been a faculty member since 2009, teaching core courses like Computer Organization and developing quantum computing curricula including the new CMPE-257 undergraduate course and CMPE-757 graduate course. Her research bridges computer architecture and quantum computing with emphasis on practical quantum circuit implementation. Her educational background includes a Bachelor of Physics and Master's in Device Physics from the University Complutense of Madrid (2002), followed by a PhD in Computer Engineering (2009) where she researched cache hierarchy in simultaneous multithreaded architectures. During her studies, she gained industry experience at Lucent Technologies and Fundetel working on integrated circuit design. Dr. Lopez Alarcon's primary research focuses on Quantum Computing and heterogeneous hardware solutions, specifically quantum circuit compilation processes, scalability challenges, and error resilience techniques. She investigates how to translate theoretical quantum algorithms into executable circuits while managing noise and resource constraints, with applications in optimization problems and physics simulations. Her work connects computer engineering principles to emerging quantum technologies. Analysis of her publication timeline shows a strategic shift from traditional computer architecture (2015-2018 cache/HLS research for GPU/heterogeneous systems) to quantum computing (2019-2021). Recent work explores quantum algorithms for combinatorial optimization (Grover's), quantum simulation of physical systems, and machine learning applications, reflecting her adaptation to the rapidly evolving quantum landscape while maintaining her architectural expertise. Her teaching excellence has been recognized through multiple awards: Kate Gleason College of Engineering Exemplary Performance in Teaching Award (2016, 2017, 2020) Computer Engineering Most Effective Teacher Award (2016) She actively mentors graduate students including Mark Danza (MS Computer Engineering candidate 2025), with whom she collaborated on quantum machine learning research featured in Quantum Zeitgeist (May 2025). She contributes to RIT's quantum information science minor launched in 2022, developing curriculum and supervising student research in this emerging field. Dr. Lopez Alarcon leads quantum computing research efforts within RIT's Department of Computer Engineering, collaborating with colleagues like Cory Merkel on quantum algorithm applications. Her work is supported through her personal research website and integration into university-wide quantum initiatives, positioning her at the forefront of academic quantum computing education and research.
Mark Oskin is an Adjunct Professor at the School of Computer Science and Engineering , University of Washington , focusing on Software & Hardware Systems . He leads the Sampa Group and collaborates on projects like HammerBlade and BlackParrot. University: University of Washington School: School of Computer Science and Engineering Department: Department of Electrical & Computer Engineering His research spans Computer Architecture , Parallel Computing , and Graph Processing , with additional expertise in Quantum Computing , Open Source Hardware , and Distributed Shared Memory . Ongoing work includes custom manycore devices for graph execution and open-source RISC-V designs. Past projects like Grappa and WaveScalar advanced distributed memory and dataflow execution. Recent publications include BlackParrot: An Agile Open Source RISC-V Multicore for Accelerator SoCs (IEEE Micro 2020) and Perceptual Compression of Video Storage and Processing Systems (SoCC 2019), reflecting trends in hardware-software co-design, quantum systems, and energy-efficient video processing. Best Paper Award , USENIX ATC 2015 IEEE Micro Top Picks , 2009 Mark has advised numerous students, including Amrita Mazumdar (IoT video compression startup), Brandon Lucia (CMU), and Steve Swanson (UC San Diego). He co-founded Corensic, a startup exploring deterministic multithreaded execution.
