Juan David Guerrero BalagueraView profile
Research Fellow
Juan David Guerrero Balaguera is a Research Fellow at Politecnico di Torino's Department of Automatic Control and Computer Science (DAUIN), affiliated with the CAD group. He holds a Ph.D. in Computer and Control Engineering from Politecnico di Torino (2024), advised by Prof. Matteo Sonza Reorda and Prof. Ernesto Sanchez. His research focuses on dependable hardware for safety-critical systems, including GPU reliability, fault tolerance, AI accelerators, and functional in-field testing. Prior to his Ph.D., he earned a Master's (2017) and Bachelor's (2013) in Electronics Engineering from Universidad Pedagógica y Tecnológica de Colombia, where he taught digital design, embedded systems, and FPGA-based image processing from 2014 to 2020. His research interests span advanced FPGA design, computational arithmetic for AI, fault effects analysis in GPUs, and reliability assessment of neural networks. Notable contributions include methods for generating self-test libraries (STLs) for GPUs, evaluating fault impacts on TCUs, and enhancing CNN robustness via dropout layer optimization. Education: Ph.D. in Computer and Control Engineering, Politecnico di Torino (2024) M.S. in Electronics Engineering, Universidad Pedagógica y Tecnológica de Colombia (2017) B.S. in Electronics Engineering, Universidad Pedagógica y Tecnológica de Colombia (2013) He has received the Ph.D. Quality Award (2023 and 2024) from Politecnico di Torino and Best Paper recognitions at DATE 2023 and DDECS 2021. His work bridges theoretical fault models with practical GPU testing methodologies, emphasizing real-world applications in AI and edge computing. Current teaching roles include collaborating on GPU programming (Master's level) and computer sciences courses (Automotive Engineering). Research collaborations involve exploring reliability trade-offs in split-computing DNNs and developing fault-aware design flows for AI accelerators.









