Professor Philip Leong is a faculty member at the University of Sydney's School of Electrical & Information Engineering, serving as Director of the Computer Engineering Laboratory. He holds a B.Sc., B.E., and Ph.D. from the University of Sydney. His academic career spans roles at institutions like the Chinese University of Hong Kong and industry collaborations with companies like ST Microelectronics and CruxML Pty Ltd. Research Interests: Leong specializes in FPGA-based solutions for high-performance computing, financial systems, medical monitoring (e.g., Parkinson's disease), and environmental forecasting. He pioneers applications in edge-based machine learning, low-latency systems, and hardware-software co-design. Key Projects : Radio Frequency Machine Learning Edge-based Training of Deep Neural Networks using FPGAs Awards : 2005 FPT Best Paper Award 2007 & 2008 FPL Outstanding Paper Awards Teaching: He instructs courses in embedded systems, computer architecture, and digital logic (e.g., ELEC3607, ELEC5741). His lab focuses on custom hardware and parallel software to address real-world challenges like financial risk modeling and climate prediction. Labs/Teams: Leads the Computer Engineering Lab, affiliated with The Net Zero Institute, Sydney Nano Institute, and the Charles Perkins Centre.
Enrique Ostúa Arangüena is an Associate Professor in the Department of Electronic Technology at the University of Seville. He is part of the Digital Research and Development group and has been involved in numerous research projects focused on microelectronics, embedded systems, and FPGA-based solutions. His work includes contributions to IoT security, real-time systems, and hardware-oriented file systems. He has led or participated in projects such as USECHIP (Microelectronics Chair), Advanced Initiation Systems for IoT, and Hardware Vorbis CODEC development. His research spans digital circuit design, low-power electronics, and FPGA implementation, with emphasis on applications like time synchronization (SNTP), cryptographic hardware (E-LUKS), and embedded system optimization. He has authored chapters in books such as Grid Computing and Program of Teaching Teams for the Training of Novice Teachers , and has presented at conferences like the IBERCHIP Workshop and IEEE Symposium on Industrial Embedded Systems. Key contributions include patents on trigonometric function calculators and hardware security modules. He has collaborated extensively with researchers like David Guerrero Martos and Julián Viejo Cortés, focusing on methodologies for teaching digital electronics and FPGA-based SOC design. His work emphasizes open-source technologies, hardware-software co-design, and practical applications in industrial control systems.
Jordi Cortadella is a Full Professor in the Department of Software at the Universitat Politècnica de Catalunya (UPC), Spain. His academic journey spans decades, with a Ph.D. in Computer Science from UPC (1987) and visiting roles at institutions like UC Berkeley and Intel Corporation. A Fellow of the IEEE (2015) and member of Academia Europaea (2013), he specializes in formal methods, concurrency theory, and asynchronous circuit design. His work bridges theoretical and applied research in EDA tools and VLSI systems. Education M.S. in Computer Science, UPC (1985) Ph.D. in Computer Science, UPC (1987) Research Interests : Cortadella's research focuses on algorithms for electronic design automation, asynchronous circuits, and formal methods. Recent publications explore Petri net decomposition, dataflow circuit verification, and ethical frameworks for research governance. His work impacts both theoretical concurrency models and practical applications like FPGA optimization and energy-efficient design. Scientific Awards : Fellow of the IEEE (2015) Member of Academia Europaea (2013) Distinction for University Research Promotion (Catalan Government, 2003) Descartes Prize Finalist (2002) Best Ph.D. Thesis at UPC (1992) National Award for Best Computer Science Student (1986)
Rocco Fazzolari is a Professor at Sapienza University of Rome's School of Engineering, Department of Electrical Engineering and Information Technology. With over 50 publications spanning from 2010 to projected 2025 works, he maintains an active research program focused on digital signal processing, hardware acceleration, and machine learning implementations. His research interests center on FPGA implementation of communication systems, with particular expertise in Residue Number System applications, QAM/PSK demodulation techniques, and reinforcement learning hardware accelerators. His work bridges theoretical signal processing concepts with practical hardware implementations, often targeting communications and control systems applications. Recent publications demonstrate increasing focus on machine learning integration with traditional signal processing techniques. Analysis of his publication trends shows consistent output across multiple venues including IEEE Access, IEEE Transactions on Circuits and Systems, and various conference proceedings. His collaborative pattern reveals a core research group including Gian Carlo Cardarilli, Luca Di Nunzio, and Marco Re, with whom he has co-authored over 45 publications each. He has also organized multiple academic conferences including the International Conference of Yearly Reports on Informatics, Mathematics, and Engineering (ICYRIME) and the Sapienza Yearly Symposium of Technology, Engineering and Mathematics. Research Recognition: Extensive publication record in IEEE journals and major conferences Organizer of multiple international academic conferences Consistent collaborative research output with established research group Fazzolari's work demonstrates strong application focus in communications systems, with recent expansion into machine learning hardware acceleration. His research group appears to maintain stable funding and productivity, with publications showing progression from fundamental digital circuit design to more complex machine learning integrated systems over the past decade.
Manikandan Palanichamy is an Associate Professor at Østfold University College, specializing in green energy transitions, smart energy systems, and emerging ICT technologies. He holds a PhD in Electronics and Telecommunications Engineering from NTNU, Norway, and has extensive international academic and industry experience. Education: PhD (2013): NTNU, Norway Master’s (2006): National Cheng Kung University, Taiwan Bachelor’s (2004): MKU, India Engineering Diploma (2001): Alagappa Polytechnic, India Research Interests: His work focuses on green energy, Industry 5.0, circular economy, IoT integration, and hardware security. He has pioneered novel CAM cell designs, path delay fault testing methodologies, and sustainable energy solutions. Recent projects include bilateral collaborations on renewable energy and smart industrial IoT systems. Publications: Over 30 peer-reviewed articles in journals like IEEE Proceedings and International Journal of Engineering and Advanced Technology. Key themes include AI integration in networks, LoRaWAN for industrial IoT, and hardware security. Awards: IEEE Best Paper Award (2006) Roles: International Coordinator at Østfold University College, managing student exchanges and partnerships. He also advises industrial projects in software development and IIoT integration. Labs/Teams: Involved in the Green Energy Research Hub and collaborates with institutions globally on projects like BioSolar Hydrogen and ReSAG (Remote Sensing for Agriculture).
Florian Ferdinand Huemer is a PostDoc Researcher at the Embedded Computing Systems department (E191-02 Faculty Council Substitute Member) within the Faculty of Informatics at Vienna University of Technology. His work focuses on fault-tolerant asynchronous circuits, delay-insensitive communication protocols, and FPGA reliability analysis. BSc , Vienna University of Technology Dipl.-Ing. , Vienna University of Technology Dr.techn. , Vienna University of Technology Key research areas include: Fault-Tolerant Computing : Designing systems resilient to transient faults and radiation effects. Asynchronous Circuits : Developing quasi-delay-insensitive logic and Muller pipelines. Embedded Metrology : Applying polarization cameras and time-to-digital converters for industrial measurements. Recent publications address: 2024 : Polarization camera-based inline thickness measurement and FPGA ring oscillator synchronization. 2023 : Mitigating single-event transients in QDI logic. 2021 : Automated fault-injection frameworks and QDI pipeline sensitivity analysis. Projects funded by the Austrian Science Fund (FWF) during 2013-2018 explored self-stabilizing Byzantine fault-tolerant algorithms. Supervisions include: Haschke (2024): QDI adder comparison Spitzer (2024): Automated fault-injection framework Schwendinger (2022): Asynchronous circuit testing tools Pircher (2022): Smart SoC testing via IJTAG Behal (2021): QDI design template fault sensitivity
Behrooz Parhami is a Distinguished Professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara, where he has been a faculty member since 1988. He previously served as Associate Dean for Academic Personnel in the College of Engineering from 2009-2012 and as Vice Chairman of the ECE Department from 1990-1992. Before joining UCSB, he was a professor at Sharif University of Technology in Tehran, Iran from 1974-1988. He received his PhD in Computer Science from UCLA in 1973. Professor Parhami's research focuses on computer arithmetic, parallel processing, and fault-tolerant computing. In computer arithmetic, he pioneered generalized signed-digit number systems as a unified framework for redundant representations. His work in parallel processing includes contributions to database processors, interconnection networks, and scalable architectures. In fault tolerance, he developed systematic data-driven methodologies for reliable hardware and software systems. He has also made significant contributions to adapting computer technology for Persian language computing. His scholarly output demonstrates consistent focus on fundamental computing principles. Recent publications show continued exploration of unconventional number systems, reliability analysis, and specialized computing architectures. His work bridges traditional computer architecture with emerging technologies including atomic-scale computing, neuromorphic systems, and novel memory technologies. His research maintains relevance through connections to both theoretical foundations and practical implementations. IEEE Life Fellow Fellow of Institution of Engineering and Technology Chartered Fellow of British Computer Society IEEE Centennial Medal (1984) Top-cited article award from Journal of Parallel and Distributed Computing (2010) IET Circuits, Devices & Systems Premium Achievement Award (2009) Sharif University Technology Association's Dr. Amin Lifetime Achievement Award (2024) Professor Parhami has graduated four PhD and numerous MS students. His teaching spans both undergraduate and graduate levels, with recent courses including ECE 1B (Puzzling Problems in Computer Engineering), ECE 252B (Computer Arithmetic), ECE 254B (Parallel Processing), and ECE 257A (Fault Tolerant Computing). He has authored six textbooks that have been widely adopted internationally, including works on parallel processing, computer arithmetic, and computer architecture. His consulting activities focus on high-performance digital system design and intellectual property issues. He is actively involved in promoting gender equity through UCSB's Men Advocating for Gender Equity (MAGE) group, which he currently chairs.
Snorre Aunet is a Professor II in the Department of Informatics at the University of Oslo, affiliated with the Faculty of Mathematics and Natural Sciences. He is a key member of the Nanoelectronics Systems Research Group and contributes to the 4DSpace project. His academic background includes a Dr. ing. from NTNU (2002) and a cand. scient. from the University of Oslo (1993). His research focuses on ultra-low-voltage and low-power mixed-signal circuits , particularly in subthreshold operation, with applications in IoT, space systems, and energy harvesting. He specializes in radiation-hardened (radhard) and defect-tolerant architectures, leveraging advanced semiconductor technologies like 22nm and 28nm FDSOI. His work integrates circuit design, microarchitecture, and reliability under extreme conditions such as radiation exposure and process variation. The recent trend in his publications shows a strong emphasis on energy-efficient VLSI design , including SRAM cells, adders, level shifters, and flip-flops operating in subthreshold regimes. He has also expanded into MEMS-based energy harvesting and hardware security, demonstrating a broad and evolving research portfolio. His collaborations span institutions and involve both theoretical modeling and practical implementation. Scientific Awards: No specific awards mentioned in the provided text. Advising and Grants: Snorre Aunet has supervised multiple students, including Somayeh Hossein Zadeh, Even Låte, and Ali Asghar Vatanjou, whose names appear as co-authors on several publications. He is involved in the 4DSpace research project, indicating active grant funding and leadership in space-related electronics research. His advising style appears collaborative, with students contributing to high-impact journals and conferences. Labs and Teams: He is a core member of the Nanoelectronics (NANO) research group at the Department of Informatics, which focuses on next-generation electronic systems. This group is engaged in cutting-edge research in nanoscale circuits, low-power design, and robust computing architectures.
Dr. Fayez Gebali is a Professor in the Department of Electrical and Computer Engineering at the University of Victoria. He holds a BSc from Cairo University, another BSc from Ain Shams University, and a PhD from the University of British Columbia. His research focuses on computer communications, digital VLSI design, signal processing, and cybersecurity. He is particularly known for contributions to networks-on-chips, hybrid communication systems (e.g., FSO/RF), and cryptographic solutions for IoT devices. Education: BSc, Cairo University BSc, Ain Shams University PhD, University of British Columbia His research interests span computer architecture , communication networks , and secure embedded systems . Recent work emphasizes digital health applications, including AI-driven medical imaging (e.g., TongueTransUNet for tongue contour segmentation) and zero-trust frameworks for healthcare data protection (ZTCloudGuard). He has also published extensively on IoT security, cryptographic algorithms, and hardware acceleration techniques. Notable contributions include pioneering work on networks-on-chips (NoC) optimization, hybrid FSO/RF transmission systems, and efficient modular multipliers for constrained devices. His publications cover over 15 years of impactful research, with a focus on bridging theoretical advancements and practical implementations in high-performance computing and cybersecurity.
Xin Zhang is a Research Staff Member and Manager at IBM T. J. Watson Research Center and an Adjunct Professor in the Department of Electrical Engineering at Columbia University since 2021. His work bridges AI hardware, power electronics, and algorithm design, focusing on energy-efficient systems for machine learning and computing. Affiliation: IBM T. J. Watson Research Center (Research Staff Member/Manager) Affiliation: Columbia University (Adjunct Professor, School of Engineering) His research interests include analog circuits, power management circuits, DC-DC converters, machine learning hardware accelerators, computer system architecture, and AI/ML-assisted EDA tools. He has pioneered AI-driven approaches for circuit topology synthesis and thermal management in hardware. Recent publications highlight innovations in chip placement optimization, secure in-memory computing for AI, and high-efficiency converters for AI SoCs. His work integrates machine learning with power electronics to address challenges in energy efficiency, security, and real-time performance. He has received prestigious recognition as an IBM Master Inventor (2023) and is an IEEE Senior Member. His editorial roles include Guest Editor for IEEE Journal on Emerging and Selected Topics in Circuits and Systems and Associate Editor for IEEE Solid State Circuits Letters. Active in academic and industry leadership, he serves on Technical Program Committees for conferences like APEC, ISSCC, and DAC, and is on the Organizing Committee for the IBM IEEE CAS/EDS AI Compute Symposium since 2019.
Jae-sun Seo is an Assistant Professor at Arizona State University's School of Electrical, Computer and Energy Engineering (ASU), joining in 2014. He previously worked at IBM T. J. Watson Research Center (2010-2013) and held internships at Intel and Sun Microsystems during his graduate studies. His research focuses on machine learning hardware , neuromorphic algorithms , and power management , with expertise in FPGA acceleration and VLSI design. Key research themes: Hardware acceleration of deep learning via FPGAs Neuromorphic computing with CMOS and resistive devices Energy-efficient integrated circuits for AI Power management techniques in high-performance processors His awards include the Samsung Scholarship (2004-2009), IBM Technical Achievement Award (2012), and NSF CAREER Award (2017). He has served on program committees for ISLPED, ISOCC, and ICCD, and reviewed for ISCAS.
Masao Yanagisawa is a Professor at Waseda University's School of Fundamental Science and Engineering, with over 25 years of academic experience since 1998. An IEEE and ACM member, he holds a Doctor of Engineering degree from Waseda University.
Tobias Grosser is an Associate Professor in the Department of Computer Science and Technology at the University of Cambridge. His research focuses on compiler technology, programming language design, and performance programming, with applications spanning hardware design, climate science, and quantum computing. He leads a research group developing innovative compiler frameworks and tools that bridge theoretical foundations with practical applications. Dr. Grosser completed his undergraduate studies in Computer Science at the University of Passau in Germany and pursued his PhD at École Normale Supérieure Paris as a Google PhD Fellow. Prior to joining Cambridge, he served as a Reader at the University of Edinburgh and held an Ambizione Fellowship at ETH Zurich. His research program centers on rethinking performance programming by re-connecting developers and compilers. He aims to make compilation more modular, predictable, automatic, and trustworthy while bringing open-source compiler innovation to increasingly diverse targets from GPUs to FPGAs and custom hardware. His work spans multiple domains including polyhedral compilation, constraint solving, quantum computing, and hardware design automation. Dr. Grosser is particularly interested in breaking down barriers between compilers and programmers by enabling their interaction through the programming language environment. His recent publications demonstrate a strong focus on compiler infrastructure development, particularly around the MLIR framework. He has pioneered work on Presburger arithmetic optimization with the FPL library, developed new intermediate representations for hardware description and quantum computing, and created tools for compiler education and prototyping like xDSL. His research shows a consistent theme of creating practical, high-performance compiler technologies that address real-world challenges across multiple domains. HiPEAC Technology Transfer Award 2021 for "Fast linear programming through transprecision computing on small and sparse data" OOPSLA 2021 Distinguished Paper Award for "FPL: Fast Presburger arithmetic through transprecision" Dr. Grosser actively mentors PhD students and postdoctoral researchers, currently supervising a team of over a dozen researchers working on various aspects of compiler technology. His group collaborates with industry partners including ARM and Xilinx, and maintains strong ties with the LLVM and MLIR open-source communities. He has secured funding for multiple research projects including work on verified compilation with Lean-MLIR, quantum compiler development, and hardware design automation. His research group operates at the intersection of multiple projects including Open-Source Electronic Design Automation, Seamless design of Smart Edge Processors, Lean-MLIR for verified compilation, FPL for fast Presburger arithmetic, and compilation frameworks for quantum computers. They maintain strong community engagement through regular Compiler Social events in Cambridge and active participation in LLVM developer meetings.
Antonio Rubio Solá is a Full Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the High Performance Integrated Circuits and Systems Design (HIPICS) group. He holds an M.S. in Industrial Engineering (1977) and a Ph.D. in Electronic Engineering (1982), both from UPC. His research focuses on semiconductor technology evolution, integrated circuit design, and memristor-based neuromorphic systems. Key interests include nanoelectronics, energy-efficient computing, and biomimetic circuits. Rubio has contributed to advancements in memristive logic, graphene nanoribbon devices, and fault-tolerant circuit architectures. His work bridges theoretical research and practical implementation, with notable contributions in neuromorphic hardware, in-memory computing, and radiation-hardened electronics. Recent publications emphasize memristor applications in biological systems emulation, stochastic resonance phenomena, and energy-efficient data processing. Rubio actively participates in Spain’s neuromorphic technology initiatives and promotes sustainable microelectronics education through digital tools. Publications are accessible via UPC FenixDoc and the HIPICS e-prints repository. His research is driven by interdisciplinary collaboration, addressing challenges in next-generation computing paradigms and emerging technologies.
Dr. Christopher Anand is an Associate Professor in the Department of Computing and Software and the McMaster School of Biomedical Engineering at McMaster University. He holds roles as Graduate Advisor for the MEng in Computing and Software and is a Fellow of IBM Canada Advanced Studies. His research spans computer science education, programming languages, compilers, and high-performance computation, with collaborations at IBM and global educational initiatives. Education: PhD in Differential Geometry. He focuses on making computing education accessible globally through projects like McMaster Start Coding and the Fondation STaBL, emphasizing design thinking and innovation. His work bridges academia and industry, addressing challenges in medical imaging, scanning electron microscopy, and educational technology. Research Interests: Includes scientific computing, optimization, and the application of design thinking in education and innovation. Notable achievements include the IBM Project of the Year Award (2018) for technology impacting IBM processors. He teaches courses such as Mobile User Interface Design and Model-Based Image Reconstruction, and his outreach efforts engage students from elementary schools to global post-secondary institutions.
