Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Swiss Federal Institute of Technology in LausanneSwitzerland
Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
Prof. Dr. Christian Plessl is a W3 Professor of High-Performance Computing at the Institute of Computer Science, University of Paderborn. He leads the Paderborn Center for Parallel Computing (PC²), a national HPC center within the NHR alliance. His roles include Director of PC², Board Member of the NHR association, and member of the Sonderforschungsbereich 901. Education: PhD (Dr. sc. ETH) in Computer Engineering, ETH Zürich (2006) MSc in Electrical Engineering, ETH Zürich (2001) Postdoc at ETH Zürich (2007–2011) Research Interests: Architecture and tools for high-performance parallel and reconfigurable computing, FPGA acceleration, quantum chemistry, scientific computing, adaptive systems, and energy-efficient HPC solutions. Key projects include EKI-App (FPGA-based neural networks), FPGA4XPCS (X-ray spectroscopy), and HighPerMeshes (unstructured grid frameworks). Publications: Over 100 peer-reviewed works, focusing on FPGA acceleration, HPC frameworks, and quantum computing. Recent trends emphasize energy-efficient neural networks, FPGA-based quantum computing, and scalable HPC algorithms. Awards: Best Paper Awards at HEART 2023, ReConFig 2012/2014 Paderborn University Research Awards (2018, 2009) SEW-EURODRIVE Student Award (2001) Grants & Projects: Principal investigator in DFG, BMBF, and EU-funded projects. Collaborates with AMD/Xilinx, Intel/Altera, and Fujitsu. Leads initiatives like PerficienCC (custom computing) and HighPerMeshes. Labs/Teams: Directs the High-Performance Computing group at PC², focusing on FPGA supercomputing and HPC infrastructure. Active in the NHR alliance for national HPC coordination.
Linghao Song is an Assistant Professor in the Department of Electrical & Computer Engineering at Yale University. His research focuses on accelerator architecture design, FPGA-based acceleration systems, and ReRAM-based computing. He is affiliated with the School of Engineering & Applied Science and holds expertise in sparse matrix processing, high-level synthesis, and task-parallel programming frameworks. Education: Ph.D. and M.S. from Duke University and University of Pittsburgh, respectively, with a B.S.E. from Shanghai Jiao Tong University. Research Interests: Song's work spans FPGA-accelerated computing, resistive memory (ReRAM) architectures for deep learning and graph processing, and high-performance sparse matrix operations. His recent projects include the TAPA framework for FPGA programming, ReFloat for iterative linear solvers, and the Sextans/Serpens accelerators for sparse matrix computations. Key Contributions: Over 20 peer-reviewed publications on topics like ReRAM-based accelerators (e.g., GraphR, PipeLayer), FPGA optimization frameworks (TAPA, RapidStream), and novel hardware designs for neural networks and graph analytics. His work emphasizes energy efficiency, scalability, and cross-domain applicability of hardware accelerators. Awards: Recipient of the Duke ECE Outstanding Dissertation Award (2021), EDAA Outstanding Dissertation Award (2020), and National Scholarship of China (2012). Labs/Teams: Leads research in FPGA acceleration and memory-based computing, collaborating on projects involving HBM integration, resistive memory architectures, and task-parallel dataflow frameworks.
Nachiket Kapre is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, Canada (2023–present). He previously held positions as Associate Professor (2016–2021) and on leave as Research Director at Xilinx Labs (AMD Research, Singapore, 2022–2023). Before that, he was an Assistant Professor at Nanyang Technological University (NTU), Singapore (2012–2016) and a Junior Research Fellow at Imperial College London (2010–2012). He earned a Ph.D. and two M.S. degrees from the California Institute of Technology (2010), and a B.E. from the University of Pune (2002). His research focuses on Concurrent and Spatial Architectures , Parallel Processing , and Communication-Centric Design , with a strong emphasis on FPGA-based acceleration for applications like machine learning, graph algorithms, and embedded systems. Key contributions include Hoplite NoC architectures and CaffePresso for deep learning acceleration. Notable awards include the FPT Best Paper Award (2024), TRETS Best Paper Award (2023), and the CASES 2016 Best Paper Award. He has led multiple grants, including NSERC Discovery Grants and A*STAR-funded projects. His advising spans 15+ students across PhD and MSc levels, contributing to FPGA toolflows, NoC design, and hardware acceleration. He has authored over 50 publications in top venues like FPGA, FPL, and ACM TRETS, and serves as a program chair for FCCM 2023. His work bridges theory and practice, emphasizing energy-efficient computing and reconfigurable systems.
Kevin Skadron is the Harry Douglas Forsyth Professor of Computer Science at the University of Virginia's School of Engineering and Applied Science, where he has been faculty since 1999. He previously served as department chair from 2012-2021 and has made significant contributions to computer architecture research. Dr. Skadron received his B.S. in Electrical and Computer Engineering and B.A. in Economics from Rice University in 1994, and his Ph.D. in Computer Science from Princeton University in 1999. He spent the 2007-08 academic year on sabbatical at NVIDIA Research. His research focuses on computer architecture, particularly novel heterogeneous processor organizations, accelerator architecture, processing in memory, and automata processing. He has pioneered work in processing-in-memory (PIM) architectures, automata processing for pattern matching, and heterogeneous computing systems. His work addresses critical challenges in thermal management, power delivery, process variations, and wear-out in modern computing systems. Current projects include Fulcrum, Gearbox, Sieve, and DRAM-CAM architectures, along with the development of the PIMeval simulation framework and PIMbench benchmark suite. Skadron's recent publications reveal a strong focus on processing-in-memory architectures, with numerous papers on PIM design, benchmarking, and applications. His research also emphasizes automata processing for pattern matching, with contributions to FPGA-based implementations and programming models. Many of his recent works address graph processing acceleration, bioinformatics applications, and memory system optimization, demonstrating the practical impact of his theoretical contributions. Dr. Skadron has received numerous accolades including the 2023 SRC/SIA University Research Award for lifetime research contributions to the U.S. semiconductor industry, the 2011 ACM SIGARCH Maurice Wilkes Award, and is a Fellow of both IEEE and ACM. He was also named a University of Virginia Teaching Fellow for 2003-04. Skadron has advised numerous graduate students, with recent PhD graduates now working at leading companies like IBM, AMD, Apple, and Black Sesame. His research has been supported by the National Science Foundation, Semiconductor Research Corporation, DARPA, and industry partners including NVIDIA, Intel, and Micron. He co-founded IEEE Computer Architecture Letters and served as editor-in-chief from 2010-2012. He is actively involved in the UVA Center for Automata Processing (CAP) and has served as director for the SRC JUMP 1.0 Center for Research on Intelligent Storage and Processing in Memory (CRISP). He is currently a member of the SRC JUMP 2.0 Center for Research on Processing in Storage and Memory (PRISM).
KAIST - Korea Advanced Institute of Science & TechnologySouth Korea
Professor Kim Jeong-ho is a distinguished faculty member in the Department of Electrical Engineering at Korea Advanced Institute of Science and Technology (KAIST), recognized globally as a pioneer in artificial intelligence semiconductor technology. He is the key architect behind High Bandwidth Memory (HBM), a core technology that enabled Korea's world-first commercialization of AI semiconductors, driving growth for industry leaders like Samsung Electronics and SK Hynix. His research focuses on semiconductor engineering with specialization in AI hardware and memory architecture. Professor Kim has established the "Next-Generation HBM Roadmap (HBM4-HBM8)" guiding technological development through 2038, while actively leading international standardization efforts to secure Korea's technological leadership in this critical field. His work bridges theoretical innovation with industrial implementation in semiconductor memory systems. Professor Kim's exceptional contributions have been recognized with: 7th Hanyang Baeknam Award in Engineering (2025) - honoring Dr. Kim Yeon-jun's legacy with 150 million won prize 8th Kang Dae-won Award in Circuits and Systems (February 2025) Over his 30-year career, he has mentored 115 master's and doctoral students while publishing 712 papers and winning 34 best paper awards. He maintains strategic collaborations with global technology leaders including Google, NVIDIA, Apple, and Tesla to advance semiconductor research and talent development. His KAIST research group focuses on next-generation memory architectures for AI applications, working closely with semiconductor industry partners to translate cutting-edge research into commercial innovations that shape global AI infrastructure.
