Find Academic Supervisors

Robert RinkerView profile

Associate Professor

• Computer Architecture
• Reconfigurable Computing
• Embedded Systems Security
• +3 more

Robert Rinker, Ph.D., is an Associate Professor and Associate Chair in the Department of Computer Science at the University of Idaho, part of the College of Engineering. His office is located in Hedlund Building 202D, and he can be reached at rinker@uidaho.edu. Rinker holds a Ph.D. in Computer Science from Colorado State University, and both Master's and Bachelor's degrees in Electrical Engineering from the University of Idaho. His teaching responsibilities include courses such as Computer Science I (CS 120), Computer Organization and Architecture (CS 150), System Software (CS 270), Advanced Computer Architecture (CS 451/551), and Real-Time Operating Systems (CS 452/552). His research focuses on reconfigurable computing, embedded systems security, computational biology pipelines, and hardware compilation techniques. Specific contributions include work on FPGA-based systems, resilient multi-core architectures, and formal verification methodologies. Rinker’s research trends emphasize the intersection of hardware-software co-design and cybersecurity, with notable contributions to VANET security and computational density optimization in embedded systems. His publications span topics from workflow automation in bioinformatics to compiler-driven FPGA optimization strategies. While no formal awards or grants are listed, his extensive academic service as Associate Chair highlights his leadership in departmental operations. He advises courses but no listed students or active lab teams are mentioned in the provided materials.

• GPU Computing
• Parallel Processing
• Computer Architecture
• +5 more

Ayşe Yılmazer Metin is an Assistant Professor in the Department of Computer Engineering at Istanbul Technical University's Faculty of Computer and Informatics. Her research focuses on computer architecture, GPU computing, and hardware security, with significant contributions to parallel processing systems and cryptographic implementations. Her educational background includes: PhD from Northeastern University (2010-2013) Degree from University of Rhode Island (2004-2007) Licence from Hacettepe University, Department of Computer Engineering (1991-1998) Dr. Yılmazer Metin's research interests center around GPU architecture and parallel computing systems. Her work addresses critical challenges in synchronization mechanisms for multi-GPU systems, power and energy measurement of embedded GPUs, and efficient implementations of cryptographic algorithms on specialized hardware. She has developed novel approaches to scope promotion in GPU environments, which significantly reduce communication overhead in multiprocessor systems. Her recent work has expanded into healthcare applications, developing privacy-preserving systems for real-time ECG monitoring and exploring homomorphic encryption techniques for secure computation. Her publication record shows a clear trajectory from fundamental GPU architecture research toward security applications and healthcare technology. Early work focused on GPU synchronization and memory management, while more recent publications demonstrate applications in secure medical systems and homomorphic encryption. This evolution reflects a strategic expansion of her core expertise in computer architecture into security-critical domains where hardware-level optimizations can provide significant advantages. Dr. Yılmazer Metin has served as Principal Investigator on multiple research projects: "Time-Critical Job Management in Multi-CPU + Multi-GPU Distributed Heterogeneous Systems" (2018-2019) "A Single-Processor GPU Architecture for More Efficient Graph Algorithms" (2018-2021) "Programmable Synchronization Architecture" (2018-2022) Her laboratory work focuses on GPU architecture and hardware security, with particular emphasis on developing efficient implementations of cryptographic algorithms on GPU platforms and optimizing graph neural network inference on heterogeneous computing systems.

• Hardware-Software Co-Design
• Compiler Design
• Embedded Systems
• +5 more

Dr. Frank Hannig is a Professor at the Department of Computer Science, Friedrich Alexander University Erlangen-Nuremberg (FAU), Germany. He serves as the Head of the Architecture and Compiler Design Group within the Hardware-Software-Co-Design department (Department 12). With a career spanning over two decades at FAU since 2003, he has established himself as a leading researcher in hardware-software co-design, compiler design, and embedded systems. Dr. Hannig received his Diploma degree in Electrical Engineering/Computer Science from the University of Paderborn in 2000, followed by his Dr.-Ing. degree in Computer Science from FAU in 2009 with a thesis on "Scheduling Techniques for High-Throughput Loop Accelerators." He completed his habilitation (Dr.-Ing. habil.) in 2018 with a thesis titled "Domain-specific and Resource-aware Computing," which qualifies him for a full professorship in the German academic system. His research focuses on hardware-software co-design, compiler design for embedded systems, reconfigurable computing, parallel systems, and machine learning acceleration. Dr. Hannig has made significant contributions to domain-specific and resource-aware computing, with applications in image processing, automotive systems, and edge AI. His work bridges the gap between high-level programming models and efficient hardware implementations, particularly for resource-constrained environments. Dr. Hannig's recent publications reveal a strong trend toward efficient machine learning deployment on embedded devices and microcontrollers, with particular emphasis on memory optimization, hardware acceleration, and low-precision computing. His research spans multiple domains including computer architecture, machine learning, and embedded systems, with a focus on practical implementations for real-world applications. Dr. Hannig serves as an Associate Editor for IEEE Embedded Systems Letters and the Journal of Real-Time Image Processing. He has organized numerous prestigious conferences including SLOHA 2021, ARC 2021, and Euro-Par 2021, demonstrating his leadership in the academic community. As an educator, Dr. Hannig teaches courses on Domain-Specific and Resource-Aware Computing on Multicore Architectures, Parallel Systems, and Embedded Systems. He has supervised numerous students through lectures, exercises, and seminars covering electronic system level design and multi-core architectures. Dr. Hannig leads several significant research projects including InvasIC (DFG Transregional Collaborative Research Centre), ExaStencils (Advanced Stencil-Code Engineering), and HBS (DFG Research Training Group on Heterogeneous Image Systems). His work with the HIPAcc open-source project has contributed to domain-specific language and compiler development for image processing applications.

Chia-Lin YangView profile

Professor

• Low-power embedded systems
• High-performance processor architecture
• Massive data storage systems
• +6 more

Chia-Lin Yang is a Professor in the Department of Computer Science and Information Engineering at National Taiwan University's College of Electrical Engineering and Computer Science. He currently serves as Director of the Delta-NTU Joint Research Lab and maintains active leadership roles in multiple research initiatives. Professor Yang's research focuses on low-power embedded systems, high-performance processor architecture, and massive data storage systems. His current work explores storage systems for big data analytics, compute-in-memory architecture design, and AI-enabled IoT. His lab, the Embedded Computing Laboratory, investigates emerging memory technologies including ReRAM and their applications in neural network acceleration and processing-in-memory architectures. His recent publication trends show a strong focus on memory systems for AI acceleration, with significant contributions to processing-in-memory architectures, ReRAM-based neural network accelerators, and storage optimization for machine learning workloads. His work bridges computer architecture, memory systems, and AI hardware acceleration, addressing critical challenges in performance, power efficiency, and reliability. Professor Yang has received numerous prestigious awards including the 2018 Outstanding Electrical Engineering Professor award, two IBM Faculty Awards (2010, 2005), and the 2009 IEEE/ACM ISLPED Best Paper Award. As an active researcher, Professor Yang serves on multiple editorial boards including ACM Transactions on Computer Architecture and Code Optimizations, ACM Transactions on Embedded Computing Systems, and IEEE Transactions on Computer-Aided Design. He maintains leadership roles in major conferences including DAC and ISLPED, demonstrating his significant contributions to the computer architecture community. His Embedded Computing Laboratory provides research opportunities in cutting-edge areas of computer architecture and memory systems, with connections to industry through the Delta-NTU Joint Research Lab and Taiwan AI Labs.

Dolly SapraView profile

Researcher

• Machine Learning
• Edge Computing
• Embedded Systems
• +8 more

Dolly Sapra is a researcher at the University of Amsterdam , affiliated with the Department of Computer Science under the Faculty of Science . Her work focuses on adaptive deep learning, secure neural inference, energy-efficient computing, and fault-aware systems. She received the IEEE/ACM CASES '24 Outstanding Reviewer Award . Her research spans Machine Learning , Edge Computing , and Embedded Systems , with a focus on Model elasticity for CNNs Privacy-preserving edge intelligence Power-efficient inference Transformer optimization Climate-aware computing . The 15 most recent articles highlight her leadership in adaptive neural architectures , secure multi-party inference , and sustainable computing , with applications in embedded systems and real-time environments .

Jose Manuel Claver IborraView profile

Professor

• Parallel and Distributed Computing
• Cloud Computing
• Video Coding
• +7 more

Dr. José Manuel Claver Iborra is a Full Professor at the Department of Computer Science, School of Engineering (ETSE-UV), University of Valencia. He holds a PhD in Computer Science (Parallel and Distributed Computing program) from the Technical University of Valencia and an MSc in Physics (specialized in Electronics and Computer Science) from the University of Valencia. As an IEEE Senior Member, he focuses on cloud computing, video coding, parallel/distributed systems, reconfigurable computing, and network protocols for real-time applications. Current Research: Cloud-based video encoding, GPU acceleration for DNA analysis, FPGA-based network protocols, and indoor localization systems Academic Leadership: Coordinator of the UV-Tirant node in the Spanish Supercomputing Network (RES) His recent publications analyze GPU-based motion estimation, heterogeneous computing for video standards (H.264/AV1), and QoS scheduling algorithms. He supervises PhD and Master's theses on sensor networks, FPGA programming platforms, and parallel applications. Scientific Awards IEEE Senior Member He has directed funded projects on cloud infrastructure, distributed video processing, and reconfigurable systems since the 1990s.

Rohan Basu RoyView profile

Assistant Professor

• Parallel Computing
• Distributed Systems
• Cloud Computing
• +3 more

Rohan Basu Roy is an Assistant Professor (tenure-track) at the University of Utah, affiliated with the Kahlert School of Computing and the SCI Institute. His research focuses on optimizing parallel and distributed computing systems, including cloud, serverless, and HPC environments, with an emphasis on sustainability and cost-effectiveness. He holds a Ph.D. in Computer Engineering from Northeastern University, advised by Prof. Devesh Tiwari. Affiliations: University of Utah (Kahlert School of Computing), SCI Institute. His research interests include scheduling algorithms, energy efficiency, and environmental sustainability in computing systems. He has pioneered open-source tools like GreenMix and ECOLIFE , widely adopted in the systems research community. Awards: ACM-IEEE CS George Michael Memorial HPC Fellowship (2023), MLCommons ML and Systems Rising Star (2023), Northeastern University Excellence in Research Award (2023). Rohan has served as a program committee member for top-tier conferences (ASPLOS, HPCA, SC) and co-chaired tracks such as AI/ML for Systems at HiPC 2025. He has also delivered invited talks at Google Brain and ParslFest 2023.

• Embedded Systems
• Real-Time Systems
• System-on-Chip Design
• +7 more

Adriano José Conceição Tavares is an Associate Professor at the School of Engineering, University of Minho, Portugal. He serves as a Senior Researcher at Centro ALGORITMI, where he is affiliated with both the IE R&D Group and the ESRG R&D Lab. His academic credentials include a PhD in Industrial Electronics from the University of Minho, a Master of Science in Information Technology from the University of Coimbra, and an undergraduate degree in Informatics from the University of Coimbra. Professor Tavares specializes in embedded systems with particular expertise in: Embedded systems modeling and design System software design System-on-chip design Real-time operating systems Hardware acceleration and FPGA design Virtualization for embedded systems IoT frameworks and protocols His publication record demonstrates a strong research trajectory in hardware-software co-design, with recent work showing an increasing integration of machine learning techniques into embedded systems. His publications span theoretical frameworks to practical implementations addressing real-time performance, resource constraints, and security challenges. Among his scholarly metrics: h-index of 18 126 publications with 1148 citations 20 publications in Q1/Q2 journals Author of a book on microcontroller programming Professor Tavares has supervised students including Miguel Ângelo Fernandes Silva and has established international collaborations through the Erasmus Program with institutions in China, Iran, Thailand, Jordan, and Cambodia. He teaches advanced courses on embedded and real-time systems modeling, compiler design, system-on-chip design, real-time operating system design, and advanced computer architectures at University of Minho.

Kunle OlukotunView profile

Professor

• Computer Architecture
• Parallel Programming
• Chip Multiprocessors
• +4 more

Kunle Olukotun is a Professor of Electrical Engineering and Computer Science at Stanford University's School of Engineering, where he has been faculty since 1991. He directs the Stanford Pervasive Parallelism Lab (PPL) and co-leads the Transactional Coherence and Consistency (TCC) project. His research focuses on computer architecture, parallel programming environments, and scalable parallel systems. Key areas include chip multiprocessors (CMPs), transactional memory systems, domain-specific languages (DSLs) for heterogeneous computing, and hardware-software co-design for machine learning workloads. His work bridges theoretical foundations with practical systems implementation. Notable contributions include the Stanford Hydra research project (one of the first chip multiprocessors with thread-level speculation), founding Afara Websystems (acquired by Sun Microsystems), and developing the Niagara processor architecture. His DSL frameworks like Green-Marl and Spatial enable efficient graph analysis and hardware acceleration. His publications reveal strong trends in parallel systems evolution: from foundational CMP research (2000s) to transactional memory (2004-2010), then DSLs for heterogeneous computing (2010-2015), and currently foundation model systems (2023-2025). Subfield analysis shows consistent focus on hardware-software co-design, sparse computation, and compiler techniques across decades. ACM Fellow (2006) for contributions to multiprocessors on a chip and multi-threaded processor design Best Paper Award at IEEE International Symposium on Workload Characteristics (IISWC '10) for EigenBench Olukotun actively mentors researchers through the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate parallelism across application domains. His projects have secured significant industry partnerships, including the acquisition of his startup Afara Websystems by Sun Microsystems. Current research focuses on compiler frameworks for foundation model systems and hardware acceleration for sparse machine learning workloads, supported by collaborations with major tech companies. He leads the Stanford Pervasive Parallelism Lab (PPL), which develops compiler and runtime systems for heterogeneous architectures. The lab's work spans DSLs, hardware acceleration, and parallel programming models, with strong industry ties to companies like NVIDIA and Google. Current initiatives include the Mosaic compiler framework and Stardust architecture for sparse tensor computation.