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Kaiyuan Yang is an Associate Professor in the Department of Electrical and Computer Engineering at Rice University, leading the Secure and Intelligent Micro-Systems (SIMS) Lab. His research focuses on low-power integrated circuits and bioelectronic implants for applications like the Internet of Everything and medical devices. He holds a B.S. from Tsinghua University (2012) and M.S./Ph.D. degrees from the University of Michigan (2017). Research Interests: Low-power digital/analog/mixed-signal systems Bioelectronics and implantable devices Hardware security and PUF design Mixed-signal computing and emerging materials Recent work emphasizes magnetoelectric-powered implants, secure backscatter communication, and in-memory computing architectures. His publications span top venues like IEEE ISSCC, IEDM, and ACM MobiCom. Awards: 2022 NSF CAREER Award 2022 IEEE Top Picks in Hardware Security 2016 IEEE SSCS Predoctoral Achievement Award Dr. Yang serves on editorial boards for IEEE TVLSI and program committees for ISSCC/CICC. His lab develops miniature, secure, and energy-efficient systems for healthcare and IoT applications.

• Low-power Integrated Circuits
• Bioelectronics
• Hardware Security
• +3 more

Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.

• Reconfigurable Computing
• FPGAs
• Electronic Design Automation
• +7 more

Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. She leads the Stanford Accelerate research group, focusing on domain-specific hardware architectures and agile hardware-software co-design. Her work emphasizes high-performance, energy-efficient accelerators for emerging technologies. Education: B.Tech. from IIT Delhi (2011), M.S. and Ph.D. from MIT (2013/2018). Postdoctoral experience includes NVIDIA Research (2018) and Amazon Visiting Academic (2023–present). Awards include the Sloan Research Fellowship (2024), NSF CAREER Award (2023), and Terman Faculty Fellowship (2018). Research Interests: Domain-specific architectures, near-memory computing, design productivity, and machine learning acceleration. Her group develops frameworks like AHA (Agile Hardware) for efficient accelerator design and compilers. Awards: Over 10 major awards, including best paper recognitions at VLSI, MICRO, and JSSC. Active roles as Associate Editor for IEEE JSSC and Program Chair for IEEE Hot Chips (2020). Advising & Teaching: Supervises multiple PhD and MS students in hardware design, CGRAs, and ML accelerators. Teaches VLSI design courses (EE271/272/372) and oversees independent studies in embedded systems and chip design. Labs & Collaborations: Affiliated with Stanford PORTAL Center, AHA Center, and SystemX Alliance. Projects include MINOTAUR (edge AI accelerator), Amber (CGRA-based SoC), and EMBER (RRAM macros).

• Domain-Specific Architectures
• Hardware/Software Co-design
• Energy-Efficient Computing
• +3 more

Bahar Asgari is an Assistant Professor in the Department of Computer Science at the University of Maryland, College Park. She holds appointments in CS, UMIACS, and ECE, and directs the Computer Architecture and Systems Lab (CASL). Her research focuses on domain-specific architecture design, near memory processing, and reconfigurable computing. Before joining UMD, she worked at Google, contributing to system optimization and memory utilization strategies. Education: Ph.D., Georgia Institute of Technology, 2021. Research Interests: Developing energy-efficient architectures for sparse problems, scientific computing acceleration, FPGA optimizations, and reconfigurable hardware systems. Her work addresses challenges in memory efficiency, parallelization, and hardware-software co-design across domains like machine learning and IoT. Key Awards: 2024 UMD Excellence in Teaching Award 2023 DOE Early Career Award Advising & Grants: Supervises 9 graduate students and leads projects sponsored by NSF, DOE, and industry partnerships. Her lab explores systolic arrays, near-data processing, and fault-tolerant computing. Labs/Teams: Directs CASL, which builds next-generation computing systems through hardware innovation and algorithm-architecture co-design.

• Computer Architecture
• Domain-Specific Architecture Design
• Near Memory Processing
• +3 more

Larry Pileggi is the Coraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU). He is also the Department Head of CMU’s ECE Department and has held prior roles at Westinghouse Research and Development and the University of Texas at Austin. His work bridges academic research and industry innovation, with co-founding ventures like Fabbrix Inc., Extreme DA, and Pearl Street Technologies. Dr. Pileggi earned his Ph.D. in Electrical and Computer Engineering from CMU (1989), following an M.S. (1984) and B.S. (1983) in Electrical Engineering from the University of Pittsburgh. His research focuses on three core areas: secure integrated circuit hardware (mitigating supply-chain threats), integrated circuits design methodologies (supporting sub-20nm CMOS and heterogeneous technologies), and power systems simulation (developing robust grid analysis tools like SUGAR). He has been recognized with numerous awards, including the prestigious 2023 Phil Kaufman Award for contributions to electronic system design, and is an IEEE Fellow. His academic leadership includes fostering maker initiatives and interdisciplinary research programs to address future challenges in energy and computing systems. Pileggi’s advising record includes over 47 Ph.D. students, many of whom collaborate with him in industry ventures. Current and past grants support his work on resilient power grids and novel memory technologies, reflecting a commitment to both theoretical and applied research. His lab, the Pileggi Lab, develops cutting-edge solutions for energy and integrated systems, emphasizing scalable simulation, secure hardware design, and next-generation memory architectures. Collaborations span institutions like ETH Zurich and industry partners in EDA and semiconductor sectors.

• Secure Integrated Circuit Hardware
• Integrated Circuits Design Methodologies
• Power Systems Simulation and Optimization
• +3 more

Sarita V Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign, where she conducts research spanning hardware, programming languages, operating systems, and applications with a focus on domain-specific systems. Her work bridges theoretical foundations and practical implementations, particularly in extended reality and heterogeneous computing. Her educational background includes a Ph.D. and M.S. in Computer Science from the University of Wisconsin-Madison (1993, 1989) and a B.Tech in Electrical Engineering from the Indian Institute of Technology Bombay (1987). Prior to joining Illinois, she served on the faculty at Rice University from 1993 to 1999. Adve's research centers on generalizable and scalable specialization for domain-specific systems, with current emphasis on extended reality (XR) systems including virtual, augmented, and mixed reality. She chairs the ILLIXR consortium to democratize XR research and developed the first fully open-source XR system (ILLIXR). Her foundational contributions include memory consistency models for C++ and Java programming languages, the Spandex coherence framework for heterogeneous systems, and software-driven approaches for hardware reliability. Her work spans hardware reliability (SWAT and RAMP projects), power management (GRACE system), and instruction-level parallelism. Recent publications reveal a strong focus on energy-efficient XR systems, hardware-software co-design for AI workloads, and resilience analysis. Her team explores rendering offload, visual-inertial odometry optimization, and compositional error injection frameworks, often targeting tradeoffs between energy, latency, and accuracy in mobile and edge environments. Fellow of the American Academy of Arts and Sciences Fellow of the ACM and IEEE ACM/IEEE-CS Ken Kennedy Award Anita Borg Institute Woman of Vision in Innovation Award ACM SIGARCH Maurice Wilkes Award Alfred P. Sloan Research Fellowship UIUC University Scholar University of Illinois Campus Award for Excellence in Graduate Student Mentoring Adve actively mentors students and has received multiple teaching awards. She co-founded the CARES movement to address discrimination in CS research events and chairs CS@Illinois CARES. Her service includes leadership roles in ACM SIGARCH (2015-2019), DARPA/ISAT study group, ACM Council, and Computing Research Association. She has secured significant funding including DARPA initiatives and Google Faculty Research Awards. She leads the ILLIXR consortium and has established collaborative research programs such as the $8.3M DARPA Joint University Microelectronics Program. Her lab focuses on open-source XR development, heterogeneous system architectures, and reliability-aware designs, with strong industry and government partnerships.

• Computer Architecture
• Extended Reality Systems
• Heterogeneous Computing
• +4 more

Ana Klimovic is an Assistant Professor at the Department of Computer Science, ETH Zürich, and Deputy Head of the Institute for Computing Platforms. She leads the Efficient Architectures and Systems Lab (EASL) and focuses on optimizing cloud computing performance and resource efficiency. Education: Ph.D. in Electrical Engineering (Stanford University), M.S. in Electrical Engineering (Stanford), B.A.Sc. in Engineering Science (University of Toronto) Previous Roles: Research Scientist at Google Brain Her research spans cloud computing, operating systems, distributed systems, and their intersection with machine learning. Key areas include cloud-native programming models, elastic storage, GPU sharing, and data pipeline optimization. The 2025-2024 articles highlight trends in serverless computing, large language model (LLM) serving, GPU optimization, and data-centric ML systems. Themes include elasticity, resource multiplexing, heterogeneous computing, and infrastructure for AI/ML workloads. Scientific Awards: Microsoft Research PhD Fellowship, Stanford Graduate Fellowship She has led research projects on ephemeral storage, distributed training automation, and cost-efficient ML preprocessing, with grants from Microsoft Research and Stanford.

• Cloud Computing
• Operating Systems
• Distributed Systems
• +4 more

Dr. Arkaprava Basu is an Associate Professor at the Indian Institute of Science (IISc), Bangalore. He received the ACM India Early Career Researcher (ECR) Award 2024 for his innovative contributions to efficient memory management in GPUs and CPUs through cross-stack software-hardware research. Affiliation: Indian Institute of Science (2018–present) Prior Roles: Full-time Research Staff at AMD Research (Austin, USA, 2014–2018) Education: PhD in Computer Science from University of Wisconsin-Madison (2013) His research focuses on optimizing AI hardware systems by integrating compiler, runtime, and OS design with hardware architecture. Collaborations include long-term consultancy with tech giants, emphasizing practical implementations of his theoretical work. Recognitions: ACM India ECR Award (2024) for "creative and impactful contributions toward efficient memory management for GPUs and CPUs"

• Computer Architecture
• Graphics Processing Units (GPUs)
• Memory Management
• +3 more

Shweta Shinde is an Assistant Professor at ETH Zürich's Department of Computer Science. She leads the Secure & Trustworthy Systems (SECTRS) group and is affiliated with the Institute of Information Security and the ZISC Center. Her research focuses on foundational and practical aspects of trusted computing, system security, and program analysis to protect devices ranging from smartphones to cloud servers. Key areas include AMD SEV-SNP, Arm CCA, Intel SGX, and hardware-software co-design for security. Dr. Shinde has made significant contributions to confidential computing, including frameworks like OpenCCA and tools for analyzing hardware vulnerabilities. Her work has been recognized with Best Paper Awards and Distinguished Paper Awards at top venues. She advises a group of PhD students, including Mark Kuhne, Supraja Sridhara, and Benedict Schlüter. Her service includes program committee roles at IEEE Security & Privacy, USENIX Security, and as Track Co-Chair for AsiaCCS 2026.

• Trusted Computing
• System Security
• Program Analysis
• +4 more

Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.

• Robust Computing
• NanoSystems
• Electronic Design Automation (EDA)
• +3 more

Vijay Raghunathan is a Professor in the Department of Electrical and Computer Engineering at Purdue University's College of Engineering. His work focuses on hardware and software architectures for embedded systems, wireless sensors for IoT, and wearable/implantable electronics with emphasis on low power design, energy harvesting, emerging memory technologies, and secure system design. Academic Rank: Professor Department: Electrical and Computer Engineering University: Purdue University Research Focus: Energy-efficient embedded systems, IoT, wearable devices His research explores low power design at both board-level and system-on-chip scales, micro-scale energy harvesting , and reliable/secure system design for medical devices. Recent work focuses on Processing-in-Sensor/Memory for battery-free AIoT devices, state space models for neural processing units, and security coprocessor integration in autonomous systems. Analysis of his publications reveals trends in energy-efficient neural network acceleration , approximate computing for edge inference , and compute-in-memory architectures . Key subfields include collaborative edge-cloud partitioning , sparse DNN accelerators , and security frameworks for medical devices. Vijay's work also addresses energy-accuracy tradeoffs in multimodal cognitive systems and intermittent computing using non-volatile memory technologies. His contributions span from microcontroller energy management to security protocols for implantable electronics.

• Embedded Systems
• Internet of Things (IoT)
• Wearable and Implantable Electronics
• +4 more

Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.

• Computer Architecture
• System-Level Design Automation
• Low Power Computing
• +3 more

Haibin Ling is the SUNY Empire Innovation Professor in the Department of Computer Science at Stony Brook University, part of the College of Engineering and Applied Sciences. His research focuses on computer vision, medical image analysis, augmented reality, and AI applications in science. He holds a Ph.D. from the University of Maryland (2006) and prior degrees from Peking University. Previously, he worked at Temple University (2008–2019) and held roles at Siemens Corporate Research, UCLA, and Microsoft Research Asia. Professor Ling's work spans biomedical imaging, AI for science, and human-computer interaction. He leads the CV Lab and collaborates with the AI Institute at Stony Brook. Awards include the NSF CAREER Award (2014), Best Student Paper (ACM UIST 2003), and IEEE Fellow (2020). He serves on editorial boards for IEEE Trans. PAMI, Pattern Recognition, and CVIU, and chairs major conferences like CVPR. His research group includes over 50 students and alumni, with active projects in tracking benchmarks (LaSOT), Leafsnap, and medical imaging tools. Notable publications address OCTA flow estimation, backdoor attacks on vision models, and topology-guided medical learning. Collaborations involve institutions like Temple University and Stony Brook's Department of Applied Mathematics and Statistics.

• Computer Vision
• Medical Image Analysis
• Augmented Reality
• +3 more

Michael O'Boyle is a Professor at the University of Edinburgh's School of Informatics, where he serves as Director of the ARM Research Centre of Excellence and the EPSRC Centre for Doctoral Training in Pervasive Parallelism. Holding an EPSRC Established Career Research Fellowship, he leads pioneering work in compiler technology for heterogeneous architectures, bridging theoretical advances with practical high-performance computing applications. Professor O'Boyle's research spans multiple cutting-edge areas including heterogeneous code discovery and optimization, neural machine translation for program synthesis, deep neural network system stack optimization, software-defined hardware, and compiler/architecture co-design. His approach integrates constraint analysis, program synthesis, and machine learning to address complex challenges in high-performance computing across diverse hardware platforms. His recent publications reveal a strong trend toward integrating machine learning with traditional compiler techniques, particularly in neural program synthesis, tensor optimization, and architecture-aware compilation. This work represents a paradigm shift in compiler design, moving from rule-based systems to learning-based approaches that can automatically adapt to diverse hardware targets. IEEE/ACM CGO 2025 Distinguished Paper Award for 'Tensorize: Fast Synthesis of Tensor Programs from Legacy Code' IEEE/ACM CGO 2024 Test of Time Award ACM GPCE 2023 Best Paper Award for 'C2TACO: Lifting Tensor Code to TACOM' ACM ASPLOS 2021 Distinguished Paper Award IEEE HPCA 2021 Best Paper Award for 'Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads' Professor O'Boyle has successfully mentored numerous PhD students who have secured prominent positions in academia (including at Cambridge, Edinburgh, Leeds, and McGill) and industry (including Meta, NVIDIA, Qualcomm, Huawei, and Microsoft). His research is supported by significant funding from EPSRC, ARM, and European projects including Bonseyes and Transmuter, demonstrating strong international recognition and industry impact. He leads the influential Compiler and Architecture Design (CArD) Group at the University of Edinburgh and is a founder of the HiPEAC Network of Excellence, which has grown into a major European initiative connecting researchers and practitioners in high-performance and embedded computing.

• Heterogeneous Code discovery and Optimisation
• Neural Machine Translation and Neural Synthesis
• Deep Neural Network system stack
• +7 more

Jian Huang is an Associate Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC), holding a 100% appointment since August 2024. He is also an affiliated Associate Professor in Computer Science and serves as the Y. T. Lo Faculty Fellow in ECE. Huang leads the Systems Platform Research Group and received his Ph.D. in Computer Science from Georgia Institute of Technology in August 2017, where his dissertation earned the College of Computing Dissertation Award. His research focuses on Computer Architecture, Memory and Storage Systems, AI Infrastructure, Distributed Systems, and Systems Security . Huang has pioneered work in sustainable AI infrastructures, modular data centers, neural processing unit virtualization, and ransomware-aware storage systems. His research has been featured in top-tier conferences including ISCA, MICRO, ASPLOS, OSDI, SOSP, and USENIX ATC, with over 50 publications and multiple patents issued worldwide. Huang's research has significant industry impact, with some work transferred into products and featured in popular media outlets including ACM CACM, TechXplore, and Science Daily. His work on non-volatile memory and storage systems has received extensive coverage, with some projects generating over 50 media reports. Among his notable achievements are the ACM SIGMICRO Early Career Award, NSF CAREER Award, IEEE Micro Top Picks (three times), USENIX Best Paper Award, and the MICRO Best Paper Runner Up in 2024. He has secured over $4.01M in grants ($11.12M with collaborators) from NSF, DARPA, Army Research Office, and industry partners. ACM SIGMICRO Early Career Award NSF CAREER Award IEEE Micro Top Picks (three times) USENIX Best Paper Award MICRO Best Paper Runner Up (2024) Google Faculty Research Award NetApp Faculty Fellowship Award Huang actively contributes to the academic community as program co-chair of NVMW'23 and organizer of HotInfra'23. He currently advises 12 Ph.D. students, 1 master student, and multiple undergraduates. His teaching innovations include developing ECE522: Emerging Memory/Storage System and revising ECE511: Computer Architecture with cutting-edge content.

• Computer Architecture
• Memory and Storage Systems
• AI Infrastructure
• +5 more