Hardware/Software Co-Design for Embedded Systems Professors and Supervisors | ApplySharif

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Chengmo YangView profile

Professor

University of DelawareUnited States

Dr. Chengmo Yang is a Professor in the Department of Electrical and Computer Engineering at the University of Delaware, with a joint appointment. She received her PhD and MSc in Computer Science from the University of California, San Diego, and a BSc in Microelectronics from Peking University, China. PhD, University of California, San Diego MSc, University of California, San Diego BSc, Peking University, China Her research focuses on enhancing security, reliability, non-volatility, and energy efficiency in embedded systems, cyber-physical systems (CPS), and Internet-of-Things (IoT). She leads the Computer Architecture, Reliability, and Security (CARES) group and has authored over 70 peer-reviewed publications. Recent publications emphasize neural network accelerators, non-volatile memory (NVM) optimization, and security frameworks for embedded systems. Her work explores fault tolerance, wear leveling, and side-channel attack mitigation in NVM-based FPGAs, STT-RAM, and SSDs. National Science Foundation Career Award (2013) University of Delaware Mid-Career Faculty Excellence in Scholarship Award (2020) Best paper award at ICESS (2019) Three best paper nominations at DAC, DATE, and GLSVLSI (2019) Dr. Yang serves as Associate Editor for IEEE TCAD and ACM TODAES. She is the Diversity & Inclusion Representative for IEEE CEDA and has organized numerous conferences including Technical Program Chair for CODES-ISSS 2022. Her lab has hosted current and former students like Fanruo Meng (PhD candidate), Fateme Hosseini (Qualcomm), and Patrick Cronin (Intel), focusing on graduate-level research in hardware security and reliability.

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Brandon M. LuciaView profile

Professor

Carnegie Mellon UniversityQatar

Brandon M. Lucia is the Kavčić-Moura Professor of Electrical and Computer Engineering at Carnegie Mellon University and CEO/co-founder of Efficient Computer Company. He leads the Abstract research group and focuses his work on the intersection of computer architecture, systems, and programming languages. Education: Ph.D. in Computer Science and Engineering, University of Washington (2013) — advised by Luis Ceze Research Focus: Brandon's research is broadly centered on intermittent computing , edge computing , and energy-efficient architectures . Two major thrusts define his current work: Intermittent Computing: Making battery-free, energy-harvesting devices programmable and reliable despite frequent power failures. Applications include medical implants, space systems, and large-scale sensing. Orbital Edge Computing: Designing nanosatellite constellations that perform on-orbit data processing, enabling low-latency, high-resolution sensing in space-constrained environments. Scientific Awards: NSF CAREER Award (2017) IEEE TCCA Young Computer Architect Award (2019) Sloan Foundation Fellowship (2021) ASPLOS 2020 Best Paper Award OOPSLA 2015 Distinguished Paper & Artifact Awards IEEE Micro Top Picks (2016, 2018 Honorable Mention) Advising & Grants: Brandon actively advises a strong cohort of Ph.D. students including Zhuo Cheng, Bradley Denby, Souradip Ghosh, Harsh Desai, Kiwan Maeng, Emily Ruppel, and others. His group is funded by the NSF (CAREER and SHF grants), the Sloan Foundation, and industry partnerships. Labs & Teams: He directs the Abstract research group at CMU ECE, which hosts interdisciplinary projects spanning hardware design, compiler construction, and system software for ultra-low-power and space-borne computing platforms.

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Tanzeem ChoudhuryView profile

Professor

Cornell UniversityUnited States

Tanzeem Choudhury is a Professor at the Jacobs Technion-Cornell Institute at Cornell Tech, specializing in Information Sciences. She co-founded HealthRhythms Inc. and directs the People-Aware Computing lab, focusing on machine learning for human activity and social network analysis. Her work pioneered the 'Reality Mining' field, leveraging mobile sensors to model social interactions. Choudhury holds a Ph.D. from MIT's Media Lab and B.S. in Electrical Engineering from the University of Rochester. Her research spans wearable tech, mental health interventions, and ubiquitous computing. Notable projects include affective touch wearables for anxiety reduction, stress detection systems (e.g., StressSense), and the BeWell app for well-being monitoring. Choudhury has been recognized as an ACM Fellow and SIGCHI Academy member, with impactful contributions to healthcare technology and sensor-based behavioral analysis. Current lab initiatives include developing closed-loop interventions for mental health, equity-driven sensing systems, and exploring AI integration in psychotherapy. She advises PhD students on topics like digital biomarkers, burnout detection in healthcare workers, and smartphone-based mental health assessment. Education: Ph.D. in Media Arts & Sciences (MIT), M.S. (MIT Media Lab), B.S. in Electrical Engineering (University of Rochester) Lab Team: Includes PhD candidates (Dan Adler, Yiran Zhao) and researchers focusing on health AI, wearable devices, and clinical applications. Major Awards: ACM Fellowship (2020), SIGCHI Academy (2018), Best Paper Awards at Ubicomp and MobileHCI conferences. Key Projects: OptoBeat (skin-tone calibrated blood oxygen sensor), EmotionCheck (anxiety intervention), and Affective Touch devices.

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Shreyas SenView profile

Associate Professor

Purdue UniversityUnited States

Shreyas Sen is the Elmore Associate Professor of Electrical and Computer Engineering at Purdue University, jointly affiliated with the School of Biomedical Engineering. He directs the Center for Internet of Bodies (C-IoB) and leads the SPARC Lab, focusing on circuits/systems for secure, energy-efficient body-centric communication and biomedical applications. Education: B.E. (Jadavpur University, 2006), M.S. & Ph.D. (Georgia Tech, 2009-2011). His research spans Human Body Communication (HBC), hardware security, IoT/IoB systems, and low-power sensing. Notable innovations include Electro-Quasistatic HBC (EQS-HBC) technology, which enables covert body-wire communication with 100x lower energy than conventional methods. Research Themes: Secure communication for medical wearables Physical layer security in IoT Ultra-low-power biosensors Side-channel attack mitigation in cryptographic ICs Publications: Over 200 papers in top venues (ISSCC, DAC, CICC, HOST) with focus on HBC systems, electromagnetic security, and biomedical circuits. Recent work explores EQS-HBC privacy properties (Nature Scientific Reports, 2019) and 350x current-domain signature attenuation for AES security (ISSCC 2020). Awards: NSF CAREER Award (2020) AFOSR Young Investigator (2016) MIT TR35 India (2018) 9 Best Paper Awards Intel Outstanding Researcher (2020) He advises over 20 students and leads industry collaborations through Ixana Inc. (founded 2020), commercializing EQS-HBC technology. Current efforts include EQS-based authentication systems and radiation dosimetry wearables.

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Hyesoon KimView profile

Professor

Georgia Institute of TechnologyUnited States

Hyesoon Kim is a Professor at the Georgia Institute of Technology , affiliated with the College of Computing and leading the HPArch research group . She co-directs the Center for Research into Novel Computing Hierarchies (CRNCH) . Her research focuses on Computer Architecture , GPU , Compilers and Runtime Systems , and Hardware Security , particularly for heterogeneous systems. Contact : hyesoon@cc.gatech.edu Location : 266 Ferst Drive, KACB 2344, Atlanta, GA Research Trends Her recent work spans RISC-V extensions for security, CUDA optimization on softcore GPUs, memory safety techniques, and energy-efficient deep learning architectures. Articles emphasize heterogeneous computing , GPU performance scaling, and IoT -oriented neural network methods. Open Source Projects She leads development of Macsim (heterogeneous architecture simulator) and Vortex (open-source GPU platform).

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Daniel W. BlissView profile

Professor

Arizona State UniversityUnited States

Daniel W. Bliss is a Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University and Director of ASU's Center for Wireless Information Systems and Computational Architectures (WISCA). With over $50 million in research funding as principal investigator from organizations including DARPA, ONR, Google, and Airbus, his work bridges theoretical foundations with practical implementations across multiple domains of wireless systems. Dr. Bliss received his educational foundation with a B.S.E.E. from Arizona State University (1989), followed by M.S. and Ph.D. degrees in Physics from the University of California-San Diego (1995, 1997). His academic journey includes significant industry experience at General Dynamics (1989-1993) and MIT Lincoln Laboratory (1997-2012) before joining ASU. His research program focuses on advanced wireless systems spanning radar, communications, precision positioning, computational architectures, and medical monitoring applications. Bliss employs information theory, estimation theory, and signal processing to develop novel system concepts with disruptive capabilities. Current research emphasizes RF convergence, integrated sensing and communications, and anticipatory medical analytics using wireless technologies, with particular focus on extracting physiological data from radar signals. Analysis of recent publications reveals a strong trend toward integrated sensing and communications systems, particularly utilizing mmWave and radar technologies for medical monitoring applications. His work increasingly bridges traditional communications and radar domains while expanding into physiological monitoring, demonstrating a clear trajectory toward convergence of wireless technologies for healthcare applications and remote vital sign detection. Dr. Bliss has received significant recognition for his contributions: Fellow of the IEEE (2015) 2021 IEEE Warren D. White Award for Excellence in Radar Engineering 2016-2017 Top 5% Teaching Award at ASU 2017 ASU Fulton Engineering Exemplar Faculty As a dedicated mentor, Dr. Bliss has supervised numerous graduate students through successful dissertation and thesis defenses across both PhD and Master's programs. His research portfolio includes substantial funding from diverse sources with over $50 million secured as principal investigator. Current projects include the $17M DARPA DASH project focused on advanced software-reconfigurable heterogeneous SoCs for next-generation RF systems, and multiple initiatives in contactless vital sign monitoring using radar technologies. Dr. Bliss leads the BLISS Lab and serves as director of WISCA, fostering interdisciplinary research in wireless systems. His team includes researchers working on distributed coherent systems, MIMO radar, RF convergence, and medical monitoring applications, with recent successes including the Making Waves team that tied for first place in the Air Force Spark Tank challenge. He has founded two startup companies: DASH Tech Integrated Circuits Company and the Big Little Sensor Company, focusing on high-performance embedded processing and small-scale radar physiological monitoring, respectively.

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Priyanka RainaView profile

Assistant Professor

Stanford UniversityUnited States

Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. She leads the Stanford Accelerate research group, focusing on domain-specific hardware architectures and agile hardware-software co-design. Her work emphasizes high-performance, energy-efficient accelerators for emerging technologies. Education: B.Tech. from IIT Delhi (2011), M.S. and Ph.D. from MIT (2013/2018). Postdoctoral experience includes NVIDIA Research (2018) and Amazon Visiting Academic (2023–present). Awards include the Sloan Research Fellowship (2024), NSF CAREER Award (2023), and Terman Faculty Fellowship (2018). Research Interests: Domain-specific architectures, near-memory computing, design productivity, and machine learning acceleration. Her group develops frameworks like AHA (Agile Hardware) for efficient accelerator design and compilers. Awards: Over 10 major awards, including best paper recognitions at VLSI, MICRO, and JSSC. Active roles as Associate Editor for IEEE JSSC and Program Chair for IEEE Hot Chips (2020). Advising & Teaching: Supervises multiple PhD and MS students in hardware design, CGRAs, and ML accelerators. Teaches VLSI design courses (EE271/272/372) and oversees independent studies in embedded systems and chip design. Labs & Collaborations: Affiliated with Stanford PORTAL Center, AHA Center, and SystemX Alliance. Projects include MINOTAUR (edge AI accelerator), Amber (CGRA-based SoC), and EMBER (RRAM macros).

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Kaiyuan YangView profile

Associate Professor

Rice UniversityUnited States

Kaiyuan Yang is an Associate Professor in the Department of Electrical and Computer Engineering at Rice University, leading the Secure and Intelligent Micro-Systems (SIMS) Lab. His research focuses on low-power integrated circuits and bioelectronic implants for applications like the Internet of Everything and medical devices. He holds a B.S. from Tsinghua University (2012) and M.S./Ph.D. degrees from the University of Michigan (2017). Research Interests: Low-power digital/analog/mixed-signal systems Bioelectronics and implantable devices Hardware security and PUF design Mixed-signal computing and emerging materials Recent work emphasizes magnetoelectric-powered implants, secure backscatter communication, and in-memory computing architectures. His publications span top venues like IEEE ISSCC, IEDM, and ACM MobiCom. Awards: 2022 NSF CAREER Award 2022 IEEE Top Picks in Hardware Security 2016 IEEE SSCS Predoctoral Achievement Award Dr. Yang serves on editorial boards for IEEE TVLSI and program committees for ISSCC/CICC. His lab develops miniature, secure, and energy-efficient systems for healthcare and IoT applications.

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Benjamin Carrison-SchaferView profile

Associate Professor

University of Texas at DallasUnited States

Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.

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Larry PileggiView profile

Professor

Carnegie Mellon UniversityQatar

Larry Pileggi is the Coraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU). He is also the Department Head of CMU’s ECE Department and has held prior roles at Westinghouse Research and Development and the University of Texas at Austin. His work bridges academic research and industry innovation, with co-founding ventures like Fabbrix Inc., Extreme DA, and Pearl Street Technologies. Dr. Pileggi earned his Ph.D. in Electrical and Computer Engineering from CMU (1989), following an M.S. (1984) and B.S. (1983) in Electrical Engineering from the University of Pittsburgh. His research focuses on three core areas: secure integrated circuit hardware (mitigating supply-chain threats), integrated circuits design methodologies (supporting sub-20nm CMOS and heterogeneous technologies), and power systems simulation (developing robust grid analysis tools like SUGAR). He has been recognized with numerous awards, including the prestigious 2023 Phil Kaufman Award for contributions to electronic system design, and is an IEEE Fellow. His academic leadership includes fostering maker initiatives and interdisciplinary research programs to address future challenges in energy and computing systems. Pileggi’s advising record includes over 47 Ph.D. students, many of whom collaborate with him in industry ventures. Current and past grants support his work on resilient power grids and novel memory technologies, reflecting a commitment to both theoretical and applied research. His lab, the Pileggi Lab, develops cutting-edge solutions for energy and integrated systems, emphasizing scalable simulation, secure hardware design, and next-generation memory architectures. Collaborations span institutions like ETH Zurich and industry partners in EDA and semiconductor sectors.

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Bahar AsgariView profile

Assistant Professor

University of Maryland, College ParkUnited States

Bahar Asgari is an Assistant Professor in the Department of Computer Science at the University of Maryland, College Park. She holds appointments in CS, UMIACS, and ECE, and directs the Computer Architecture and Systems Lab (CASL). Her research focuses on domain-specific architecture design, near memory processing, and reconfigurable computing. Before joining UMD, she worked at Google, contributing to system optimization and memory utilization strategies. Education: Ph.D., Georgia Institute of Technology, 2021. Research Interests: Developing energy-efficient architectures for sparse problems, scientific computing acceleration, FPGA optimizations, and reconfigurable hardware systems. Her work addresses challenges in memory efficiency, parallelization, and hardware-software co-design across domains like machine learning and IoT. Key Awards: 2024 UMD Excellence in Teaching Award 2023 DOE Early Career Award Advising & Grants: Supervises 9 graduate students and leads projects sponsored by NSF, DOE, and industry partnerships. Her lab explores systolic arrays, near-data processing, and fault-tolerant computing. Labs/Teams: Directs CASL, which builds next-generation computing systems through hardware innovation and algorithm-architecture co-design.

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Shweta ShindeView profile

Assistant Professor

ETH ZurichSwitzerland

Shweta Shinde is an Assistant Professor at ETH Zürich's Department of Computer Science. She leads the Secure & Trustworthy Systems (SECTRS) group and is affiliated with the Institute of Information Security and the ZISC Center. Her research focuses on foundational and practical aspects of trusted computing, system security, and program analysis to protect devices ranging from smartphones to cloud servers. Key areas include AMD SEV-SNP, Arm CCA, Intel SGX, and hardware-software co-design for security. Dr. Shinde has made significant contributions to confidential computing, including frameworks like OpenCCA and tools for analyzing hardware vulnerabilities. Her work has been recognized with Best Paper Awards and Distinguished Paper Awards at top venues. She advises a group of PhD students, including Mark Kuhne, Supraja Sridhara, and Benedict Schlüter. Her service includes program committee roles at IEEE Security & Privacy, USENIX Security, and as Track Co-Chair for AsiaCCS 2026.

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Vijay RaghunathanView profile

Professor

Purdue UniversityUnited States

Vijay Raghunathan is a Professor in the Department of Electrical and Computer Engineering at Purdue University's College of Engineering. His work focuses on hardware and software architectures for embedded systems, wireless sensors for IoT, and wearable/implantable electronics with emphasis on low power design, energy harvesting, emerging memory technologies, and secure system design. Academic Rank: Professor Department: Electrical and Computer Engineering University: Purdue University Research Focus: Energy-efficient embedded systems, IoT, wearable devices His research explores low power design at both board-level and system-on-chip scales, micro-scale energy harvesting , and reliable/secure system design for medical devices. Recent work focuses on Processing-in-Sensor/Memory for battery-free AIoT devices, state space models for neural processing units, and security coprocessor integration in autonomous systems. Analysis of his publications reveals trends in energy-efficient neural network acceleration , approximate computing for edge inference , and compute-in-memory architectures . Key subfields include collaborative edge-cloud partitioning , sparse DNN accelerators , and security frameworks for medical devices. Vijay's work also addresses energy-accuracy tradeoffs in multimodal cognitive systems and intermittent computing using non-volatile memory technologies. His contributions span from microcontroller energy management to security protocols for implantable electronics.

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Rakesh KumarView profile

Professor

University of Illinois Urbana-ChampaignUnited States

Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.

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Michael O'BoyleView profile

Professor

University of EdinburghUnited Kingdom

Michael O'Boyle is a Professor at the University of Edinburgh's School of Informatics, where he serves as Director of the ARM Research Centre of Excellence and the EPSRC Centre for Doctoral Training in Pervasive Parallelism. Holding an EPSRC Established Career Research Fellowship, he leads pioneering work in compiler technology for heterogeneous architectures, bridging theoretical advances with practical high-performance computing applications. Professor O'Boyle's research spans multiple cutting-edge areas including heterogeneous code discovery and optimization, neural machine translation for program synthesis, deep neural network system stack optimization, software-defined hardware, and compiler/architecture co-design. His approach integrates constraint analysis, program synthesis, and machine learning to address complex challenges in high-performance computing across diverse hardware platforms. His recent publications reveal a strong trend toward integrating machine learning with traditional compiler techniques, particularly in neural program synthesis, tensor optimization, and architecture-aware compilation. This work represents a paradigm shift in compiler design, moving from rule-based systems to learning-based approaches that can automatically adapt to diverse hardware targets. IEEE/ACM CGO 2025 Distinguished Paper Award for 'Tensorize: Fast Synthesis of Tensor Programs from Legacy Code' IEEE/ACM CGO 2024 Test of Time Award ACM GPCE 2023 Best Paper Award for 'C2TACO: Lifting Tensor Code to TACOM' ACM ASPLOS 2021 Distinguished Paper Award IEEE HPCA 2021 Best Paper Award for 'Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads' Professor O'Boyle has successfully mentored numerous PhD students who have secured prominent positions in academia (including at Cambridge, Edinburgh, Leeds, and McGill) and industry (including Meta, NVIDIA, Qualcomm, Huawei, and Microsoft). His research is supported by significant funding from EPSRC, ARM, and European projects including Bonseyes and Transmuter, demonstrating strong international recognition and industry impact. He leads the influential Compiler and Architecture Design (CArD) Group at the University of Edinburgh and is a founder of the HiPEAC Network of Excellence, which has grown into a major European initiative connecting researchers and practitioners in high-performance and embedded computing.

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