Find Academic Supervisors

Sabur H BaidyaView profile

Assistant Professor

• Autonomous Systems
• Cyber-Physical Systems
• Internet-of-Things (IoT)
• +4 more

Sabur H Baidya is an Assistant Professor in the Department of Computer Science and Engineering at the University of Louisville's J.B. Speed School of Engineering. He leads the Autonomous Intelligent Mobile Systems Lab (AIMS Lab) and is affiliated with the Louisville Automation & Robotics Research Institute (LARRI). His research focuses on autonomous systems, cyber-physical systems, IoT, edge computing, and distributed intelligence. Education: B.S. in Communication Engineering, West Bengal University, 2007 M.S. in Computer Science, University of Texas at Dallas, 2013 Ph.D. in Computer Science, University of California, Irvine, 2019 Research Interests: His work integrates sensing, communication, and computing systems to develop intelligent distributed systems. Key areas include IoT security, optimization of edge computing architectures, and autonomous drone/robotics applications. He explores machine learning techniques for resource-constrained environments and cybersecurity in containerization platforms. Awards & Recognition: No specific awards listed, though his research has been published in top-tier venues across autonomous systems, IoT, and cybersecurity domains. Advising & Grants: While no student names or grant details are provided, his lab actively engages in collaborative projects with industry partners like Nokia Bell Labs and Huawei, and academic collaborations at Rutgers WINLAB and UC San Diego. Labs & Teams: Directs the AIMS Lab, collaborating with the Louisville Automation & Robotics Research Institute (LARRI) to advance robotics and automation technologies. His work also intersects with the Jacobs School of Electrical and Computer Engineering (UCSD) and WINLAB (Rutgers).

Sean ChoiView profile

Assistant Professor

• Computer Networking
• Programmable Hardware
• Machine Learning Infrastructure
• +3 more

Sean Choi is an Assistant Professor in the Department of Computer Science and Engineering at Santa Clara University. He holds a Ph.D. in Electrical Engineering from Stanford University (2020), M.S. in Computer Science from Stanford (2013), and a dual B.S. in Computer Science and Business Economics & Management from Caltech (2011). His research focuses on programmable network hardware, including smartNICs, and their applications in machine learning, blockchain, and cloud computing. Education: Ph.D. in Electrical Engineering, Stanford University (2020) M.S. in Computer Science, Stanford University (2013) B.S. in Computer Science & Business Economics, California Institute of Technology (2011) Research Interests: Programmable Network Switches, SmartNIC Acceleration, Cloud Infrastructure, Serverless Computing, Blockchain Optimization, and Privacy-Preserving Machine Learning . Recent Work: Explores leveraging programmable hardware for low-latency machine learning inference, blockchain scalability via NIC-assisted consensus, and privacy-preserving federated learning through homomorphic encryption offload. His NSF-funded project develops ultra-low-latency ML systems using programmable networks. Awards: NSF CRII 2023 Award Hewlett Packard Enterprise Grant Labs/Teams: Leads research on network programmability and hardware acceleration within Santa Clara University's School of Engineering. Collaborates with industry on data center network optimization and cloud infrastructure projects.

• Computer Engineering
• Hardware Security
• Artificial Intelligence
• +3 more

Jaan Raik is a Tenured Full Professor and Head of the Centre for Dependable Computing Systems at Tallinn University of Technology (TalTech), Department of Computer Systems. His research focuses on hardware reliability, fault tolerance in embedded systems, and secure computing architectures. Key areas include fault-resilient deep neural network accelerators, approximation methods for DNNs, and vulnerability assessment in hardware-software systems. He leads the Centre for Dependable Computing Systems, which explores advanced reliability engineering techniques for modern computing systems. His work integrates formal verification, machine learning, and hardware design to address challenges in embedded systems, RISC-V processors, and edge AI chips. Notable contributions include frameworks like Saffira for DNN accelerator reliability assessment and innovative methods for assertion-based verification. Research interests span fault diagnosis, approximation computing, and security-aware architectures. He frequently publishes at top venues such as IEEE European Test Symposium and DDECS, with recent focus on resilient neural networks, cache leakage detection (CLD), and hardware Trojan mitigation. Collaborations include industry partnerships for practical deployment of fault-tolerant systems and academic initiatives to standardize reliability assessment methodologies. His work bridges theoretical computer engineering with applied solutions for real-world systems.

Gabriela NicolescuView profile

Professor

• Cybersecurity for Avionics
• Security by Design for Cyber-Physical Systems
• Advanced Programming Models for Avionic Multi and Many-Core Systems
• +11 more

Gabriela Nicolescu is a Professor at Polytechnique Montréal , affiliated with the Department of Computer Engineering and Software Engineering and the LAMA-WeST (Web, Semantics and Text) research group. Her work focuses on design methodologies , programming , and security for advanced systems integrating 3D SoCs , optical networks , and heterogeneous technologies . Education: B.Sc. and M.Sc., Politehnica Bucharest Ph.D., Institut National Polytechnique de Grenoble (2002), awarded Best Thesis in Microelectronics Research Interests include cybersecurity for avionics , security by design for cyber-physical systems , advanced programming models for multi-core systems , and modeling/simulation of heterogeneous systems . She has contributed to fields like optical networks on chip , real-time embedded systems , and edge computing security . Recent Publications highlight her leadership in all-optical neural networks , formal verification , and security for avionic systems . Her work spans machine learning-driven intrusion detection , photonic integrated circuits , and ontology-based cybersecurity frameworks . Scientific Awards: Best Thesis in Microelectronics, Institut National Polytechnique de Grenoble (2002) Student Supervision encompasses doctoral and master’s theses in areas such as multi-core RTOS , security in autonomous systems , AI-based penetration testing , and performance optimization in avionics . Current advisees include Felipe Magalhaes , Julien Carayol , and Kacem Khaled , while completed supervision includes A. S. Shahnejat Bushehri and Rami Zrelli . She is actively involved in collaborative research projects addressing national cybersecurity priorities and safer aircraft design , as highlighted in media outlets like The Globe and Mail and Science-Presse .

Aastha MehtaView profile

Assistant Professor

• Systems Security
• Data Privacy
• Operating Systems
• +3 more

Aastha Mehta is a Tenure-Track Assistant Professor in the Computer Science Department at the University of British Columbia (UBC), affiliated with the Systopia Lab and the Security and Privacy Group. Her research focuses on systems security, data privacy, and distributed systems, particularly in cloud and edge platforms. She teaches courses such as CPSC 538M (Systems Security) and CPSC 317 (Introduction to Computer Networking). Research Interests: Her work spans systems security, network privacy, ICS security, and privacy-preserving technologies. Key projects include compliance tools for serverless applications (Growlithe), network side-channel mitigation (NetShaper), and epidemic risk mitigation systems leveraging Bluetooth beacons. Received NCC Funding for ICS security research (2024) Faculty Teaching Awards (UBC) Advising: Currently supervises PhD and MSc students like Yayu Wang, Angela DeMarco, and Satvik Vemuganti. Collaborates with researchers from MPI-SWS, UofT, and UBC ECE on security and privacy projects. Service: Serves on program committees for CCS 2025, ASPLOS 2025, and Oakland S&P. Organized mentoring programs at SOSP and OSI.

• Computer Architecture
• Domain-Specific Architectures
• Reconfigurable Computing
• +4 more

Trevor Mudge is a Professor in the Department of Computer Science and Engineering at the University of Michigan. His work focuses on domain-specific architectures, reconfigurable computing, and energy-efficient processors. He leads a research group emphasizing collaborative innovation, with weekly meetings to discuss progress and foster interdisciplinary collaborations with institutions like MIT and Technion. His research interests include hardware-software co-design, near-memory processing, and accelerators for graph analytics and machine learning. He advocates for student autonomy in research direction, encouraging them to explore novel ideas while providing mentorship through frequent one-on-one interactions and 'extreme editing' sessions for manuscript refinement. Dr. Mudge actively supports student internships aligned with their research, particularly in industry partnerships that enhance their academic work. His publications reflect a strong emphasis on specialized architectures for wireless communication, sparse matrix computations, and low-power embedded systems. His group's approach to advising prioritizes flexibility, with communication channels like email, Slack, and virtual whiteboards enabling continuous feedback. Vacations and time away are accommodated with advance notice, emphasizing student well-being and productivity balance.

Ali ZamaniView profile

Research Fellow

• Biomedical Engineering
• Medical Imaging
• Antenna Design
• +3 more

Dr. Ali Zamani is an Honorary Research Fellow at the School of Electrical Engineering and Computer Science, The University of Queensland. His research focuses on biomedical engineering, medical imaging, and electromagnetic systems. He holds a PhD in frequency-based microwave medical imaging from UQ (2018). His work combines antenna design, signal processing, and machine learning to develop innovative diagnostic tools for conditions like hepatic steatosis, stroke, and pulmonary edema. Key projects include the HepNet neural network for liver disease detection and a portable electromagnetic brain scanner for acute stroke diagnosis. Research interests span microwave medical imaging, wearable sensors, and electromagnetic tomography. His contributions include over 45 peer-reviewed publications and patents on medical imaging probes and systems. Collaborations involve interdisciplinary teams in biomedical engineering, electrical engineering, and clinical medicine. His recent publications highlight advancements in AI-driven diagnostics, non-invasive imaging techniques, and hardware innovations for clinical applications. He has pioneered electromagnetic systems for 3D head imaging and torso scanning, with emphasis on real-time and portable solutions.

Juan David Guerrero BalagueraView profile

Research Fellow

• AI Accelerators
• GPU Reliability
• Fault Tolerance
• +7 more

Juan David Guerrero Balaguera is a Research Fellow at Politecnico di Torino's Department of Automatic Control and Computer Science (DAUIN), affiliated with the CAD group. He holds a Ph.D. in Computer and Control Engineering from Politecnico di Torino (2024), advised by Prof. Matteo Sonza Reorda and Prof. Ernesto Sanchez. His research focuses on dependable hardware for safety-critical systems, including GPU reliability, fault tolerance, AI accelerators, and functional in-field testing. Prior to his Ph.D., he earned a Master's (2017) and Bachelor's (2013) in Electronics Engineering from Universidad Pedagógica y Tecnológica de Colombia, where he taught digital design, embedded systems, and FPGA-based image processing from 2014 to 2020. His research interests span advanced FPGA design, computational arithmetic for AI, fault effects analysis in GPUs, and reliability assessment of neural networks. Notable contributions include methods for generating self-test libraries (STLs) for GPUs, evaluating fault impacts on TCUs, and enhancing CNN robustness via dropout layer optimization. Education: Ph.D. in Computer and Control Engineering, Politecnico di Torino (2024) M.S. in Electronics Engineering, Universidad Pedagógica y Tecnológica de Colombia (2017) B.S. in Electronics Engineering, Universidad Pedagógica y Tecnológica de Colombia (2013) He has received the Ph.D. Quality Award (2023 and 2024) from Politecnico di Torino and Best Paper recognitions at DATE 2023 and DDECS 2021. His work bridges theoretical fault models with practical GPU testing methodologies, emphasizing real-world applications in AI and edge computing. Current teaching roles include collaborating on GPU programming (Master's level) and computer sciences courses (Automotive Engineering). Research collaborations involve exploring reliability trade-offs in split-computing DNNs and developing fault-aware design flows for AI accelerators.

Benedict HerzogView profile

Researcher

• Energy-Efficient Systems
• Operating Systems
• Embedded Systems
• +3 more

Benedict Herzog is a Researcher at the Bochum Operating Systems and System Software (BOSS) group at Ruhr-Universität Bochum (RUB). Previously, he was part of the Department of Computer Science 4 (Distributed Systems and Operating Systems) at Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU). His work focuses on energy-efficient systems, operating systems optimization, and embedded computing. Herzog holds a Master's degree in Computer Science from FAU, where his thesis explored energy demand estimation using artificial neural networks, and a Bachelor's degree in Energy-aware error correction in wireless sensor networks. His research interests span energy-aware computing, system software design, and machine learning applications for optimizing edge and embedded systems. He actively participates in academic activities, serving as a reviewer for conferences like TECS, SBESC, and EMSOFT. Herzog has taught courses such as 'Systemnahe Programmierung in C' and 'Energy-Aware Computing Systems' at FAU, and advised multiple students on topics ranging from interrupt handling overhead to Meltdown/Spectre mitigation impacts. Key technical contributions include frameworks for energy measurement integration (EnergyBudgets), system-call aggregation (AnyCall), and automated OS configuration optimization. His work bridges hardware-software co-design challenges in energy efficiency, with applications in edge computing and real-time systems.

Ozgur SinanogluView profile

Professor

• Hardware Security
• Integrated Circuit Design
• VLSI Circuits
• +7 more

Ozgur Sinanoglu is a Professor of Electrical and Computer Engineering at New York University Abu Dhabi (NYUAD) and a Global Network Professor at NYU Tandon School of Engineering. He holds a B.S. in Electrical and Electronics Engineering and Computer Engineering from Bogazici University (1999), and an M.S. and Ph.D. in Computer Science and Engineering from UC San Diego (2001, 2004). His research focuses on hardware security, design-for-trust, and VLSI circuit reliability. Education: B.S., Electrical and Electronics Engineering & Computer Engineering, Bogazici University, 1999 M.S., Computer Science and Engineering, UC San Diego, 2001 Ph.D., Computer Science and Engineering, UC San Diego, 2004 Research Interests: Design-for-Security in VLSI circuits Logic locking and hardware obfuscation Hardware Trojans and side-channel attacks Secure chip manufacturing and testing His work has led to over 200 publications and 20 patents. He directs the NYUAD Center for Cybersecurity and the Design-for-Excellence Lab, funded by NSF, DoD, Intel, and Mubadala Technology. Awards include the NYUAD Distinguished Research Award (2021) and induction into the UAE's Mohammed bin Rashid Academy of Scientists (2021). Grants and Leadership: Lead PI on NSF and DoD-funded projects Directed ACM ASIACCS 2017 in Abu Dhabi Associate Editor for IEEE TIFS, TETC, and JETC Labs and Teams: Center for Cybersecurity (CCS) Design-for-Excellence Lab (DfX)

Yuke WangView profile

Assistant Professor

• Deep Learning Systems
• High-Performance Computing
• Parallel Programming
• +3 more

Yuke Wang is an incoming Assistant Professor at Rice University's Department of Computer Science starting Fall 2025. He earned his Ph.D. in Computer Science from the University of California, Santa Barbara (2024) and B.E. in Software Engineering from the University of Electronic Science and Technology of China (2018). His research focuses on optimizing deep learning systems through compiler and hardware co-design, with expertise in GPU acceleration, parallel computing, and distributed training. Education: Ph.D., UC Santa Barbara (2024); B.E., UESTC (2018). Professional experience includes postdoctoral research at Amazon AWS AI and internships at NVIDIA, Microsoft Research, and Alibaba DAMO Academy. Research interests include accelerating graph neural networks (GNNs), recommendation systems, and large language models (LLMs). He has developed frameworks like GNNAdvisor, MGG, and ZEN to enhance efficiency and scalability in deep learning workloads. His work has been recognized with awards such as the NVIDIA Graduate Fellowship and ACM PACT Student Research Competition. Awards include NVIDIA Graduate Fellowship (2022-2023), UCSB Dissertation Fellowship (2023), and multiple best paper nominations. He actively serves on program committees for top conferences like OSDI, ASPLOS, and ICS. Current hiring: Seeking graduate/undergraduate students for projects in deep learning systems, compiler optimization, and GPU acceleration. Collaborates closely with industry partners including NVIDIA and Amazon.

• Computer Architecture
• Computer Security
• Quantum Computing
• +5 more

Assoc Prof Anupam Chattopadhyay is an Associate Professor in the College of Computing & Data Science at Nanyang Technological University (NTU), Singapore. He also holds a courtesy appointment in the School of Physical & Mathematical Sciences. His research focuses on computer architecture, security, design automation, and quantum computing. Anupam received his PhD from RWTH Aachen University in 2008, followed by roles at CoWare R&D and RWTH Aachen as a Junior Professor before joining NTU in 2014. Education: B.E., Jadavpur University, India MSc, ALaRI, Switzerland PhD, RWTH Aachen University, Germany Research Interests: Anupam’s work spans quantum computing, hardware security, AI security, post-quantum cryptography, and emerging technologies. His contributions include novel high-level synthesis techniques for cryptography, reliability estimation flows for embedded processors, and exploration of coarse-grained reconfigurable architectures. His research has been featured in major outlets like The Economist and Asian Scientist. Awards: Borcher's plaque (2008) for outstanding doctoral dissertation Nomination for Best IP Award (ACM/IEEE DATE 2016) Nomination for Best Paper Award (International Conference on VLSI Design 2018) Advising & Grants: Anupam leads a team of over 20 researchers, overseeing projects funded by various grants. He has advised numerous doctoral students and collaborates with institutions like Temasek Labs and the Indian Statistical Institute. Labs & Teams: His research group focuses on advanced topics in secure computing, quantum-resistant systems, and hardware-software co-design, leveraging cutting-edge tools and platforms for next-generation technologies.

Lam Siew KeiView profile

Associate Professor

• Edge Intelligence
• FPGA Acceleration
• Computer Vision
• +5 more

Assoc Prof Lam Siew Kei is an Associate Professor at the School of Computer Science and Engineering (SCSE), Nanyang Technological University (NTU), Singapore, and leads the Hardware and Embedded Systems Lab (HESL). He holds the role of Assistant Dean (Admissions and Outreach) in the College of Computing and Data Science (CCDS). His research focuses on edge intelligence, custom computing techniques, FPGA acceleration, and embedded systems security. Lam earned his BASc, MEng, and PhD from NTU’s School of Computer Engineering and has held visiting research roles at institutions like Imperial College London and RWTH Aachen. Education: Bachelor of Applied Science (BASc), School of Computer Engineering, NTU Master of Engineering (MEng), School of Computer Engineering, NTU Doctor of Philosophy (PhD), School of Computer Engineering, NTU Research Interests: Edge intelligence and domain-specific architectures FPGA-based acceleration for visual SLAM and deep learning Hardware security and embedded systems reliability Real-time visual analytics and low-complexity algorithms Grants and Projects: Principal Investigator of grants like FL-SLAM (Ministry of Education), Road User Trajectory Prediction (Desay SV Automotive), and Energy-Efficient Architecture (DSO National Laboratories) Co-Principal Investigator in Urban Mobility Grand Challenges and Cyber-Hardware Assurance programs Students and Collaborations: Supervised numerous PhD, Master’s, and undergraduate students across topics like FPGA acceleration, visual SLAM, and embedded security. Collaborates with industry partners like Desay SV Automotive and DSO National Laboratories. Labs and Teams: Leads the Hardware and Embedded Systems Lab (HESL), focusing on custom computing and edge AI applications.

Chao ChenView profile

Assistant Professor

• High performance computing
• Numerical linear algebra
• Numerical PDE
• +3 more

Chao Chen is an Assistant Professor in the Department of Mathematics at North Carolina State University (NC State), where he has been since 2023. His research focuses on developing efficient algorithms for matrix computations, with applications ranging from solving partial differential equations to analyzing large high-dimensional datasets. Prior to this, he was a postdoctoral researcher at The University of Texas at Austin’s Oden Institute, working with George Biros and Gunnar Martinsson. He earned his PhD in Computational and Mathematical Engineering (ICME) from Stanford University in 2018, advised by Eric Darve. He also holds an MS from Stanford’s ICME (2014) and a BS in Information and Computational Mathematics from Nankai University (2012). Education: PhD in Computational and Mathematical Engineering, Stanford University, 2018 MS in Computational and Mathematical Engineering, Stanford University, 2014 BS in Information and Computational Mathematics, Nankai University, 2012 Research Interests: Chen’s work emphasizes high-performance computing, numerical linear algebra, and randomized algorithms. He develops methods to reduce computational complexity and enhance performance on modern hardware. His applications span computational physics, data science, and machine learning. Notably, he has contributed to fast multipole methods, hierarchical solvers, and preconditioners for large-scale systems. Teaching: Chen teaches courses such as Linear Analysis (MA 303), Mathematics of Scientific Computing (MA 402), Linear Transformations and Matrix Theory (MA 523), and Theory of Matrices (MA 723). His courses emphasize theoretical foundations and practical applications, often incorporating computational tools like MATLAB and LaTeX. Presentations: He has presented at conferences worldwide, including SIAM Annual Meetings, Supercomputing Conferences, and specialized workshops on numerical linear algebra and fast solvers.

Andrew B. KahngView profile

Professor

• VLSI Physical Design
• Design for Manufacturability
• AI in Chip Design
• +3 more

Andrew B. Kahng is a Distinguished Professor of Computer Science & Engineering and Electrical and Computer Engineering at the University of California San Diego. He leads research in VLSI physical design, AI-driven chip design, and semiconductor roadmapping. His work focuses on advancing EDA tools, such as the OpenROAD Project and TILOS AI Institute, to address challenges in chip design automation. He has authored over 500 publications, holds 35 patents, and is a Fellow of both ACM and IEEE. His accolades include the 2019 Ho-Am Prize in Engineering. Key affiliations include the VLSI CAD Laboratory and leadership roles in international conferences like DAC and ISPD. Kahng has mentored numerous students, contributing to their academic and professional success. His research spans from foundational algorithms (e.g., placement and routing) to industry collaboration through initiatives like the OpenROAD Project, which provides open-source tools for chip design. Recent advancements include ML integration in EDA, pathfinding frameworks (PROBE3.0), and contributions to the semiconductor technology roadmap. His work emphasizes open-source ecosystems and interdisciplinary collaboration to drive innovation in microelectronics.