Find Academic Supervisors

• Hyperdimensional Computing
• Neuromorphic Hardware
• In-Memory Computing
• +3 more

Paul R. Genssler is a Dr.-Ing. researcher at the Chair of AI Processor Design (AI-Pro) within the Technical University of Munich (TUM), actively advancing hardware solutions for artificial intelligence under Prof. Hussam Amrouch. His work bridges computer engineering and emerging technologies, focusing on overcoming fundamental limitations in conventional computing architectures through brain-inspired paradigms. His research spans critical domains in next-generation computing: Hyperdimensional Computing for robust pattern recognition and bioinformatics applications Neuromorphic and In-Memory Computing architectures for energy efficiency Reliability engineering for emerging memory technologies (FeFET, etc.) Quantum computing support systems including cryogenic embedded electronics Machine learning-driven transistor aging prediction and mitigation Analysis of his 15 most recent publications (2023-2024) reveals a dominant trend toward hyperdimensional computing as a unifying framework for addressing reliability challenges in emerging technologies. His work consistently integrates in-memory computing techniques to bypass von Neumann bottlenecks while targeting real-world applications like genome matching and unsupervised learning. A significant portion focuses on error-resilient implementations for unreliable nanoscale devices, demonstrating exceptional cross-stack expertise from transistor physics to algorithm design. As a core member of TUM's AI Processor Design group affiliated with the Munich Institute of Robotics and Machine Intelligence (MIRMI), Genssler collaborates extensively on projects spanning cryogenic quantum control systems, FPGA-based AI resilience, and monolithic 3D integration. The team operates at the intersection of semiconductor physics, computer architecture, and machine learning, with strong industry connections evident through publications at DATE, ASP-DAC, and ICCAD.

• Security Engineering
• Hardware Security
• Post-Quantum Cryptography
• +4 more

Prof. Tim Güneysu is a full Professor and Head of the Security Engineering department at the Faculty of Computer Science, Ruhr-Universität Bochum. He serves as Vice Dean for Strategy and Finances (since 2023) and previously as Speaker of the Horst-Görtz Institute for IT-Security (2020-2023). His academic journey includes roles as Associate Professor at the University of Bremen (2015-2017) and Assistant Professor at Ruhr-Universität Bochum (2011-2015). He also holds positions at the German Research Center for Artificial Intelligence (DFKI) and has conducted postdoctoral research at UMass Amherst. His research focuses on Security-by-Design principles, CAD for Security, and countermeasures against physical attacks. He emphasizes efficient cryptographic implementations and system-level hardware security. Key areas include post-quantum cryptography, side-channel resistant designs, and secure embedded systems. He has contributed over 200 publications in top venues, with recent work on FPGA-based cryptographic accelerators, secure hardware extensions (e.g., KeyVisor), and post-quantum algorithms for IoT. His research themes include agile signature acceleration, fault attack mitigation, and hardware-software co-design for security. Notable projects include CONVOLVE (edge-AI security) and QuantumRISC (quantum-safe systems). His work bridges theoretical cryptography with practical hardware implementations, emphasizing real-world security applications.

Heiner GiefersView profile

Professor

• Cloud Computing
• Hardware Acceleration
• Field-Programmable Gate Arrays
• +7 more

Heiner Giefers is a Professor for Cloud Computing at the Department of Computer Science and Natural Sciences at Southwestphalia University of Applied Sciences since 2018. Prior to this position, he worked as a Research Staff Member at IBM Research - Zürich (2013-2018), focusing on hardware acceleration in cloud environments, implementation of big data algorithms on FPGAs, and development of hardware platforms for approximate and in-memory computing. Dr. Giefers received his doctorate (Dr. rer. nat.) from Universität Paderborn in 2012 with a dissertation titled "Design and Programming of Reconfigurable Mesh based Many-Cores." His academic journey at Universität Paderborn includes serving as an Academic Council Member (Akademischer Rat a.Z.) from 2008-2013 and as a Scientific Staff Member from 2006-2012, where he taught digital technology and computer architecture. Professor Giefers' research focuses on energy-efficient computing, particularly through hardware acceleration using FPGAs for cloud and AI workloads. His work spans cloud computing infrastructure, hardware-software co-design, approximate computing, in-memory computing, and energy-efficient implementations of machine learning algorithms. He has made significant contributions to the field of reconfigurable hardware for high-performance computing applications. His recent publications show a strong trend toward applying hardware acceleration techniques to artificial intelligence and machine learning workloads, with a particular focus on energy efficiency. His work bridges the gap between theoretical computer science and practical hardware implementation, often resulting in patented technologies that address real-world computing challenges in cloud environments. Best Paper Award for "Stochastic Matrix-Function Estimators: Scalable Big-Data Kernels with High Performance" (2016) Best Paper Award Nomination for "Energy-Efficient Stochastic Matrix Function Estimator for Graph Analytics on FPGA" (2016) Best Paper Award Nomination for "Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system" (2014) Best Paper Award Nomination for "A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier" (2010) Professor Giefers actively supervises numerous Bachelor's and Master's students, with over 50 completed theses covering topics from machine learning and cloud computing to IoT systems and hardware acceleration. He leads the "Energy-efficient AI" project (eki), which aims to increase the energy efficiency of AI systems through approximation techniques for FPGA implementation. Additionally, he collaborates with Prof. Dr. Christian Plessl on the "Digital teaching materials with Jupyter Notebooks" project, creating interactive learning materials that integrate teaching content, program code, and results into a single document. His work extends to practical applications through multiple patents related to FPGA implementations, neural networks, and memory systems, demonstrating his commitment to translating research into real-world solutions.

• Electronic Design Automation (EDA)
• Computer Architecture
• Embedded Systems
• +5 more

Prof. Wolfgang Ecker is a Professor at the Technical University of Munich (TUM), affiliated with the Chair of Design Automation within the TUM School of Computation, Information and Technology . His research focuses on Electronic Design Automation (EDA), RISC-V processor architectures, and hardware-software co-design. He leads projects advancing EDA tools for embedded systems, neural network acceleration, and formal verification methodologies. Ecker's work bridges machine learning techniques with traditional EDA challenges, addressing topics like energy-efficient AI inference and automated documentation generation. His contributions span compiler optimization, FPGA implementations, and fault analysis in digital systems. Recent research highlights include contributions to the TRISTAN project for RISC-V ecosystem development, model-driven architecture frameworks, and AI-driven timing analysis. He actively collaborates on open-source EDA tools and explores Rust-based embedded systems development. Ecker’s lab emphasizes practical applications in edge computing and automotive microcontroller safety, with a strong emphasis on interdisciplinary collaboration across TUM’s CIT School. His publications (15 most recent listed) reflect a focus on EDA tool innovation, processor design, and leveraging machine learning for hardware optimization. While no specific awards are mentioned, his involvement in ERC-funded projects and leadership in international collaborations underscores his academic impact.

Alexander WildView profile

Researcher

• Security Aspects of FPGAs
• Side-Channel Analysis
• Physical Unclonable Functions
• +3 more

Dr. Alexander Wild is a former researcher at Ruhr-University Bochum's Faculty of Computer Science, affiliated with the Horst Görtz Institute for IT-Security. He completed his Diploma in 'Security in Information Technology' (2006–2012) and held a PhD position (2012–2016) at the Chair for Embedded Security. His research focuses on FPGA security, side-channel analysis, and physical unclonable functions (PUFs). Education: PhD in Embedded Security, Ruhr-University Bochum (2012–2016) Diploma in Security in Information Technology, Ruhr-University Bochum (2006–2012) Research interests include securing FPGAs against side-channel attacks, designing PUF-based authentication mechanisms, and optimizing hardware security countermeasures. His work bridges hardware design with cryptographic applications, emphasizing practical implementations on reconfigurable systems. His publications (e.g., automated EM probe repositioning, GliFreD duplication schemes) highlight contributions to FPGA-based security primitives and PUF reliability. He has collaborated with institutions like the Horst Görtz Institute and co-authored works presented at conferences such as HOST, CHES, and FPL. Affiliated with the Emmy Noether Group and involved in projects like the CAVE research initiative, he emphasizes interdisciplinary approaches to hardware security challenges.

• Digital Signal Processing (DSP)
• Field-Programmable Gate Arrays (FPGA)
• Machine Learning Hardware Acceleration
• +13 more

Gian Carlo Cardarilli is a researcher specializing in digital hardware design and machine learning acceleration. His work focuses on FPGA implementations, Residue Number System (RNS) architectures, and reconfigurable computing for applications in wireless communication, edge AI, and fault-tolerant systems. Key collaborations with institutions like IEEE and ACM through publications. Active in translating theoretical algorithms into practical hardware solutions for real-time systems. Research interests include: Optimizing deep learning models for heterogeneous platforms. Developing radiation-hardened memory systems. Creating energy-efficient signal processing architectures. Advancing reconfigurable functional units for embedded processors. His article analyses span fields like Quantum Cellular Automata , Variable Fractional Delay Filters , and RNS-Based Position Estimation , reflecting a trend toward adaptive, low-power, and domain-specific hardware.

• Fractional-Order Systems
• Chaotic Systems
• Field-Programmable Gate Array (FPGA) Implementations
• +5 more

Ahmed Gomaa Radwan is a Professor at Cairo University's Department of Engineering Mathematics and Physics, Egypt. His research spans fractional-order systems , chaotic dynamics , FPGA implementations , and bio-impedance modeling , with numerous publications in IEEE Access, Microelectronics Journal, and Circuits Systems Signal Processing. Key collaborators include Lobna A. Said , Wafaa S. Sayed , and Ahmed Soltan . His work emphasizes chaos-based encryption , fractional calculus , and hardware accelerators for real-world applications. Publications highlight trends in fractional-order chaotic systems , memristor technology , and secure image processing , often involving CNTFET designs and nonlinear resonators .

Zhe WangView profile

Researcher

• Image Processing
• Computer Vision
• Embedded Systems
• +3 more

Zhe Wang is a Researcher at the Computational Imaging Systems department within the University of Stuttgart, Germany. Their work focuses on real-time image processing, data compression, and FPGA-based hardware architectures. Research Interests Real-time video/image compression Perceptual coding with JND models Parallel decoding architectures Embedded systems for high-throughput applications FPGA design for multimedia processing Publications Highlight Recent work spans FPGA-accelerated super-resolution, marker-free variable-length coding, and perceptual compression techniques. These contributions emphasize hardware efficiency, visual quality preservation, and high-speed data processing.

Heiko HinkelmannView profile

Professor

• Embedded Systems
• Wireless Sensor Networks
• Energy Efficiency in Computing
• +3 more

Prof. Dr.-Ing. Heiko Hinkelmann is a Professor at Frankfurt University of Applied Sciences and serves as a member of the FUTURE AGING Research Center office since 2016. Based in Building 8, Room 114, he leads initiatives in developing innovative assistance technology with emphasis on safety, trustworthiness, and user-friendliness for aging populations. His research spans embedded systems design and optimization across multiple domains: Hardware/software co-design of energy-efficient embedded systems Wireless Sensor Networks for real-time monitoring Field Programmable Gate Array (FPGA) implementation Digital circuit and camera system development End-to-end energy analysis from hardware to data processing The FUTURE AGING Research Center provides laboratory infrastructure for prototyping and practical validation of these systems, focusing on early-stage integration of safety and usability requirements in assisted living applications.

• Embedded Machine Learning
• Adaptive Embedded Systems
• Knowledge Distillation
• +3 more

Julian Hoever, M.Sc., is a research associate in the Department of Intelligent Embedded Systems at the University of Duisburg-Essen's Faculty of Computer Science since June 2024. His work bridges academic research and industrial application through projects like ZaKI.D, focusing on AI accessibility for regional companies. Bachelor's in Applied Computer Science, University of Duisburg-Essen Master's in Cyber-Physical Systems, University of Duisburg-Essen (2024) His research centers on knowledge distillation and precomputable neural networks for FPGAs , enabling efficient AI models. This aligns with the ZaKI.D project 's goal of transferring AI expertise to industry via small-scale initiatives and training. Julian's recent publication in Sensors explores configurable soft sensors for fluid flow estimation, highlighting his expertise in adaptive embedded systems. Projects like IoT Garage and Elastic AI further demonstrate his focus on practical AI implementation in resource-constrained environments.