Prof. Hayden Kwok Hay SO is an Associate Professor at the University of Hong Kong (HKU), affiliated with the Department of Electrical and Electronic Engineering. He currently serves as Acting Director of the School of Innovation and previously co-directed the Computer Engineering Program. His research focuses on reconfigurable computing systems, FPGA-based architectures, and their applications in AIoT, medical imaging, and high-performance computing. He holds a B.S., M.S., and Ph.D. in Electrical Engineering and Computer Sciences from UC Berkeley (1998–2007). Prof. So has been recognized with awards such as the IEEE-HKN Teaching Award (2021), Croucher Innovation Award (2013), and multiple teaching excellence awards. He leads the Computer Architecture & System Research Lab (CASR) and co-founded the Joint Lab on Future Cities (JLFC). His work spans FPGA overlay architectures, graph processing systems, and hardware-software co-design for efficient computing. Key research contributions include advancements in FPGA-based reconfigurable systems, sparse dataflow architectures, and medical imaging accelerators. He has secured grants for projects like 'Advanced machine vision guided aquatic surface vehicles' and 'Efficient and Productive Parallel Data Processing in Hybrid FPGA-CPU Clusters.' Prof. So has advised numerous students and researchers, contributing to over 150 peer-reviewed publications. His current projects explore AI hardware acceleration, neuromorphic computing, and FPGA-driven solutions for big data challenges.
Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.
Chita R. Das is a Professor at Pennsylvania State University, known for extensive contributions in computer architecture, machine learning, and high-performance computing. Their research focuses on optimizing hardware-software co-design for edge computing, cloud infrastructure, and energy-efficient systems. Key areas include FPGA acceleration, GPU optimization, and serverless computing frameworks. Das collaborates frequently with institutions like AMD and Intel, addressing challenges in parallel computing and distributed systems. Their work bridges theoretical advancements with practical applications in recommendation systems, bioinformatics, and real-time video processing. Research interests span across hardware acceleration techniques, cloud resource management, and sustainable computing. Notable projects include adaptive training frameworks for intermittent power environments and neural-augmented game streaming for mobile platforms. Das's publications often address performance bottlenecks in modern architectures and propose novel solutions for latency and energy efficiency. Recent articles highlight innovations in serverless computing cost optimization, low-bandwidth VR streaming, and FPGA-based bioinformatics tools. Their contributions are characterized by interdisciplinary approaches combining computer architecture with machine learning and embedded systems.
Hadi Esmaeilzadeh is an Associate Professor at the University of California, San Diego in the Department of Computer Science and Engineering . He previously served as an Assistant Professor at Georgia Tech (2013-2017) and holds the Halicioğlu Chair in Computer Architecture . As founder/director of the Alternative Computing Technologies (ACT) Laboratory and associate director of UCSD's Center for Machine Integrated Computing and Security (MICS) , his research drives cross-stack solutions for next-generation computer systems. Early tenure recipient at UCSD Coined the term "dark silicon" in computer architecture Developed Tabla/DnnWeaver open-source frameworks Research Interests span: Approximate Computing Neural Acceleration FPGA/ASIC Hardware Design Machine Learning Systems Dark Silicon Challenges Security/Privacy in Accelerated Systems Scientific Recognition : 4 CACM Research Highlights 4 IEEE Micro Top Picks Distinguished Paper Award (HPCA 2016) Inducted to ISCA Hall of Fame (2018) Teaching : Developed courses on accelerator design (CSE 240D) and alternative computing (CS 8803 ACT) Advocates for hands-on FPGA-based learning in Processor Design with FPGAs courses
Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.
Professor Grahame Holmes is an Honorary Professor in the School of Engineering at RMIT University, Australia. His expertise spans electrical energy conversion, smart energy systems, renewable energy integration, power electronics, and grid infrastructure. He focuses on advancing technologies for sustainable energy storage, grid stability, and high-efficiency power conversion. Research Interests : Electrical and Electronic Engineering, Communications Technologies, Power Electronics, Renewable Energy Systems, and Grid Integration Solutions. His work emphasizes practical applications such as hydrogen energy storage systems, grid-interactive inverters, and modular multilevel converters. Recent Contributions : Prof. Holmes has published extensively on topics like advanced PWM techniques, resonant current controllers, and DC transformer designs. His research bridges theoretical advancements with real-world implementations, addressing challenges in smart grid stability and high-frequency power conversion. Advising & Grants : Supervised projects include 'Hydrogen Energy Storage System for Nanogrid' (2015) and 'Synchronised Control of Grid-Interactive Inverters' (2015). While specific grant details are not listed, his work aligns with major themes in sustainable energy research. Labs & Collaborations : Engages in collaborative research through RMIT's facilities, focusing on hardware-software co-simulation frameworks and FPGA-based real-time systems.
Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.
Professor Ryan Ko is a leading academic in Cyber Security at the University of Queensland (UQ), serving as Chair and Director of the UQ Cyber Research Centre, Director of Research at the School of Electrical Engineering and Computer Science, and a member of UQ's Academic Board. He holds a BEng (Computer Engineering) and PhD from Nanyang Technological University, Singapore. His research focuses on data provenance, industrial control systems (ICS) security, privacy-preserving technologies, and AI-driven cybersecurity solutions. Ko has pioneered initiatives such as the UQ Cyber Centre, interdisciplinary cybersecurity education programs (MCyber, PGDipCyber), and the Oceania Cybersecurity Challenge. He has attracted over AUD 20 million in competitive grants as lead investigator, including the NZ$12.2M STRATUS project. Ko’s work spans industry and policy, including advisory roles with INTERPOL, governments, and NGOs. He has authored over 100 publications, contributed to ISO standards (e.g., ISO/IEC 21878), and co-founded cybersecurity startups. Awards include Fellowships from the Australian Computer Society and Queensland Academy of Arts and Sciences, and the CSA Ron Knode Service Award. Education: Bachelor of Engineering (Computer Engineering) (Hons.), Nanyang Technological University (2005) PhD in Computer Science, Nanyang Technological University (2011) Awards: Fellow, Australian Computer Society (2016) Fellow, Queensland Academy of Arts and Sciences (2020) Young Professional Award, Singapore Government (2018) Grants & Leadership: AUD 20M+ lead investigator grants; NZ$12.2M STRATUS project (2014–2018) Established UQ Cyber Centre (2019) and NZ’s first cybersecurity graduate program (2012) His research emphasizes returning data control to users, with applications in agriculture, energy, and critical infrastructure. Ko’s contributions include patents, open-source tools (e.g., Kali Linux), and frameworks like TrustCloud for cloud accountability.
Vyas Sekar is the Tan Family Professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU), with a courtesy appointment in the Computer Science Department. He is affiliated with CyLab and co-directs the Future of Enterprise Security initiative. His research focuses on networking, cybersecurity, distributed systems, and IoT security, with an emphasis on data-driven approaches and network verification. Education: Ph.D. in Computer Science (2010) from CMU; B.Tech. from IIT Madras (President of India Gold Medal recipient). Professional roles include Chief Scientist at Conviva and co-founder of Rockfish Data. Research Interests: Cybersecurity, network security, software-defined networking (SDN), IoT security, DDoS defense, privacy-preserving data sharing, and network performance optimization. Recent work includes developing tools like Pigasus (FPGA-accelerated intrusion detection), Nomad (cloud side-channel mitigation), and frameworks for anomaly detection in IoT networks. Articles Trends: Recent publications address advanced threats like LLM-driven network attacks, stealthy automotive network exploits (CANDid), and optical-layer DDoS defenses. Emphasis on practical solutions (e.g., SketchPlan for telemetry, Pryde for firewall evasion detection). Awards: ACM SIGCOMM Test of Time Award (2022), IIT Madras Young Alumni Achiever Award (2022), Intel Outstanding Researcher Award (2021), and NSF CAREER Award (2016). Recognized for contributions to intrusion prevention, network security, and IoT resilience. Grants & Projects: Led NSF-funded ONSET project (optical-layer DDoS defense), CyLab's Secure IoT Initiative, and collaborations with industry partners like Intel, Facebook, and Nokia Bell Labs. Advises graduate students in cybersecurity and networking. Labs & Teams: Active contributor to CyLab, co-developer of frameworks like Lumos (hidden IoT device detection) and KalKi (IoT security platform). Engages in interdisciplinary research across CMU’s Robotics Institute and Software Engineering Institute.
Patrick Mitran is a full-time Professor at the University of Waterloo's Department of Electrical and Computer Engineering, within the Faculty of Engineering. His research focuses on advanced wireless communication systems, including 5G/6G technologies, millimeter-wave and sub-THz communication, digital predistortion techniques, MIMO systems, and beamforming architectures. He leads projects addressing challenges in transmitter linearization, network resource allocation, and hardware-efficient signal processing. Key research interests include optimizing frequency multiplier-based transmitters, mitigating inter-cell interference in massive MIMO networks, and developing algorithms for reconfigurable intelligent surfaces (RIS). His work often intersects hardware design, signal processing, and network optimization, with applications in next-generation wireless infrastructure. Recent publications highlight innovations in ultrawideband signal generation for 6G testing, practical RIS configurations, and FPGA-based real-time digital predistortion implementations. His contributions emphasize both theoretical advancements and practical system-level solutions. Dr. Mitran's research group collaborates on cutting-edge topics such as hybrid NOMA in multi-cell networks, adaptive coding modulation for Gaussian channels, and interference decoding strategies. His work has been published in top-tier journals and conferences, reflecting a sustained impact on modern wireless communication technologies.
Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.
Dr. Ivan Puddu is a Researcher affiliated with the Institute for Information Security at ETH Zürich. His work focuses on advancing cybersecurity, particularly in the realms of Trusted Execution Environments (TEEs), hardware security, and privacy-preserving technologies. He explores vulnerabilities in modern computing systems, including attacks on enclave-based security mechanisms and side-channel exploits. His research also addresses distributed systems, blockchain, and FPGA-accelerated architectures, aiming to enhance system sovereignty and data integrity. Notable contributions include studies on code confidentiality in TEEs, disaggregated memory systems, and mitigating security threats in low-power networks.
Arrvindh Shriraman is an Associate Professor and Program Director of Software Systems at Simon Fraser University's School of Computing Science in Surrey. His research focuses on energy-efficient software, multicore memory systems, and optimizing hardware/software interfaces for parallel programming. He holds a Ph.D. (2010) and M.S. (2006) in Computer Science from the University of Rochester, and a B.Eng. (2004) from the University of Madras. He teaches courses on parallel programming and energy-conscious software design. His research interests include synchronization mechanisms for domain-specific architectures, cache optimization, and FPGA-based acceleration. He has contributed to frameworks like Mu-grind for HLS-generated RTL instrumentation and TAPAS for parallel accelerator generation. Notable projects include RANGE-BLOCKS for synchronization in domain-specific systems and TapeFlow for gradient computation in neural networks. His work emphasizes real-time verification of autonomous systems and safety-critical trajectory planning for underwater vehicles. Shriraman collaborates closely with the Tangent Lab, exploring cutting-edge solutions in hardware-software co-design and embedded systems. His teaching and research bridge theoretical computer science with applied engineering challenges, addressing scalability, efficiency, and safety in modern computing systems.
Professor David Thomas holds the position of Professor in Computer Engineering at the University of Southampton's Electronics and Computer Science Department. His research focuses on the intersection of software and hardware, particularly leveraging FPGAs for novel digital architectures and event-driven computing. He has a notable academic trajectory, having previously served as a Lecturer and Senior Lecturer at Imperial College London before joining Southampton in 2021. Dr. Thomas is actively involved in supervising PhD students and contributes to interdisciplinary research projects funded by the EPSRC, such as the SONNETS initiative exploring scalable event-triggered systems. Education: BSc in Computer Science (Imperial College London), PhD in Digital Architectures (Imperial College London). Postdoctoral roles included Research Associate and Research Fellow at Imperial's Department of Computing. Research Interests: Event-driven computing, FPGA-based systems, high-level synthesis, and high-performance computing. His work emphasizes practical implementations of theoretical models, such as custom processors and application-specific accelerators. Current projects include optimizing random number generation for FPGAs and exploring meta-programming techniques for hardware design. Advising and Grants: Supervises multiple PhD students in areas like neuromorphic computing and algorithm optimization. Active in securing funding for distributed system architectures and FPGA-based solutions. Labs/Teams: Member of the Cyber Physical Systems research group. Collaborates with interdisciplinary teams on projects like POETS (Partially Ordered Event-Triggered Systems) for large-scale parallel computing.
