Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Marco Platzner is a Professor for Computer Engineering at Paderborn University , Germany. He serves as the Dean of Research for the Faculty of Computer Science, Electrical Engineering and Mathematics and heads the Department of Computer Science. Previously, he held research positions at ETH Zurich, Stanford University, GMD (now Fraunhofer IAIS), and Graz University of Technology. Education: Diploma and PhD in Telematics (Graz University of Technology, 1991 and 1996), Habilitation in Hardware-Software Co-Design (ETH Zurich, 2002) Research Interests focus on reconfigurable computing, approximate computing, self-* computing, and embedded systems. His work addresses hardware security, FPGA design, and sustainable AI in data centers. Current projects include energy-efficient AI through deep neural network approximation for FPGAs (EKI-App) and lifecycle sustainability of socio-technical systems (SAIL). Publication Trends show expertise in FPGA security, approximate circuit synthesis, robotics, and hardware acceleration. Collaborations span robotics (ROS 2 integration), AI (transformer optimization), and cybersecurity (Trojan detection). Scientific Awards: ACM SIGDA Hall of Fame (2020) Significant Paper Award (FPL 2015) Best Paper Awards at IEEE ISVLSI (2024), ARC (2018), IEEE ReConFig (2015), and others Weierstraß Prize for Teaching (2008) Leadership Roles include membership in the board of Paderborn Center for Parallel Computing (PC2) and the Jenny Aloni Centre for Early Career Researchers. He has contributed to EU FP7 FET project EPiCS and German priority programs on embedded systems and organic computing.
Holger Fröning is a full professor at Heidelberg University’s Institute of Computer Engineering (ZITI), where he leads the Hardware and Artificial Intelligence (HAWAII) Lab. His research focuses on embedded machine learning , high-performance computing , and hardware-software co-design , with emphasis on resource efficiency, power optimization, and emerging architectures like analog , photonic , and resistive memory systems. He has held leadership roles including Managing Director of ZITI (2023–present) and Dean of Studies for Computer Science (2019–2022) , and has collaborated with institutions such as NVIDIA Research, Chinese Academy of Sciences, and Graz University of Technology. Research Trends : His recent publications explore Bayesian neural networks , green machine learning , analog computing noise mitigation , and GPU/FPGA optimization . Articles highlight photonic computing for AI , memory-efficient training , and hardware-aware DNN compression . Scientific Awards : 2025 HiPEAC Paper Award (Nature Computational Science) 2014 Google Faculty Research Award Multiple Best Paper Awards (IPDPS, ICPP, ECML-PKDD workshops) Leadership & Service : Organized workshops (WEML, ITEM, F4HD), chaired tracks at EuroPar and ISC, and served on program committees for ICPR, ECAI, and FPL. Education & Affiliations : PhD and MSc from University of Mannheim (2007/2001). Sponsors include DFG, FWF, FFG, NVIDIA, SAP, and XILINX.
Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.
Hadi Esmaeilzadeh is an Associate Professor at the University of California, San Diego in the Department of Computer Science and Engineering . He previously served as an Assistant Professor at Georgia Tech (2013-2017) and holds the Halicioğlu Chair in Computer Architecture . As founder/director of the Alternative Computing Technologies (ACT) Laboratory and associate director of UCSD's Center for Machine Integrated Computing and Security (MICS) , his research drives cross-stack solutions for next-generation computer systems. Early tenure recipient at UCSD Coined the term "dark silicon" in computer architecture Developed Tabla/DnnWeaver open-source frameworks Research Interests span: Approximate Computing Neural Acceleration FPGA/ASIC Hardware Design Machine Learning Systems Dark Silicon Challenges Security/Privacy in Accelerated Systems Scientific Recognition : 4 CACM Research Highlights 4 IEEE Micro Top Picks Distinguished Paper Award (HPCA 2016) Inducted to ISCA Hall of Fame (2018) Teaching : Developed courses on accelerator design (CSE 240D) and alternative computing (CS 8803 ACT) Advocates for hands-on FPGA-based learning in Processor Design with FPGAs courses
Soheil Salehi is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Arizona, with a joint appointment in Systems and Industrial Engineering. He is the Director of the Privacy-preserving, Intelligent, and Secure Computing (PRISM) Lab, established in August 2022. Prior to this, he was an NSF-Sponsored Computing Innovation Fellow and Postdoctoral Research Fellow at the University of California, Davis. Ph.D., Electrical and Computer Engineering, University of Central Florida, 2020 M.S., Electrical and Computer Engineering, University of Central Florida, 2016 B.S., Isfahan University of Technology, Iran, 2014 Dr. Salehi's research focuses on the intersection of hardware, AI, and security. His work spans hardware and AI-enabled security in IoT , Generative AI for hardware design and security , neuromorphic and biologically-inspired AI hardware , emerging spin-based devices , reconfigurable architectures , low-power VLSI circuits , and digital twins and mixed reality for semiconductor workforce development . He also explores the application of Generative AI in personalized education . His recent publications, spanning 2023–2025, reveal a strong trend toward integrating AI and machine learning into hardware security and design. Key themes include automated secure IC design flows , AI-driven hardware obfuscation , firmware and side-channel attack analysis , security in neuromorphic and spiking neural networks , and educational frameworks using digital twins and generative models . His work appears in top venues like DAC, ICCAD, USENIX Security, IEEE TCAS-I, and ISCAS. Outstanding Reviewer Award, IEEE/ACM Design Automation Conference (DAC), 2023 Best Presentation of the Symposium Award, UC Davis Postdoctoral Research Symposium, 2021 UCF Excellence by a Graduate Teaching Assistant (University-Level), 2016 Nominated for 30-under-30 Award, UCF, 2020 Nominated for Postdoctoral Research Excellence Award, UC Davis, 2022 Dr. Salehi has secured significant research funding as PI and Co-PI, including a $300K NSF SaTC EAGER grant on Generative AI-based Personalized Cybersecurity Tutor, a $174,000 University of Arizona PIF Award, and multiple RII grants totaling over $198K. He has also received industry funding from CHEST. He actively mentors students and leads the PRISM Lab, which focuses on privacy-preserving and intelligent secure computing. His service includes roles as Technical Program Committee (TPC) Member and Session Chair at premier conferences such as DAC, ICCAD, CCS, NDSS, and GLSVLSI. The PRISM Lab, under his direction, conducts cutting-edge research in secure and intelligent hardware systems, with applications in IoT, edge computing, and workforce development. The lab emphasizes interdisciplinary collaboration and innovation in both research and education.
Professor Tulika Mitra is the Dean of the School of Computing and Vice Provost (Special Projects) at the National University of Singapore (NUS). She holds the Provost’s Chair Professor in the Department of Computer Science and has been instrumental in shaping academic policies and strategic initiatives at NUS since joining in 2001. PhD in Computer Science, Stony Brook University (2000) M.E. in Computer Science, Indian Institute of Science (1997) B.E. in Computer Science, Jadavpur University (1995) Her research focuses on hardware-software co-design for energy-efficient computing systems, particularly in real-time embedded systems, heterogeneous architectures, and AI accelerators. She leads major research programs such as the NRF Competitive Research Programme on Low-Power Edge Accelerators and the MOE Tier-3 Programme on Green AI , collaborating with industry leaders like ARM, AMD, and Meta. Her recent publications highlight innovations in CGRA optimization , sparse attention mechanisms , photonic-digital hybrid architectures , and low-power ML inference . These works often integrate compiler techniques, architectural design, and real-time constraints for edge computing applications. Scientific Awards : ESWEEK Test-of-Time Award (2022), ACM SIGDA Distinguished Service Award, IEEE CEDA Outstanding Service Recognition Award, Teaching Excellence Award (2006), and multiple best paper recognitions. Education Leadership : Spearheaded the Computer Engineering (CEG) Programme at NUS, a joint initiative between Engineering and Computing. As a mentor , she has supervised over 25 PhD students , many now in prominent academic or industrial roles. Her research group eCO Lab focuses on embedded computing challenges, while her grant collaborations include projects on 5G base stations, reconfigurable architectures, and IoT-optimized SoCs.
Hadi Esmaeilzadeh is an Associate Professor at the University of California, San Diego in the Department of Computer Science and Engineering . He leads the Alternative Computing Technologies (ACT) Laboratory and serves as Associate Director of the Center for Machine Integrated Computing and Security (MICS) . Previously, he was an Assistant Professor at Georgia Institute of Technology. Ph.D., Computer Science and Engineering, University of Washington (2013) Research focuses on computer architecture , machine learning acceleration , and approximate computing His work has produced 15+ publications spanning IEEE Micro Top Picks , CACM Research Highlights , and ISCA . Key projects include: Tabla : Cross-stack ML acceleration framework DnnWeaver : Open-source DNN acceleration platform Major honors include: IEEE TCCA Young Computer Architect Award ISCA Hall of Fame Qualcomm Innovation Fellowship Georgia Tech PURA Award Teaching roles: CSE 141: Introduction to Computer Architecture CSE 240D: Accelerator Design for Deep Learning CSE 240A: Principles of Computer Architecture
Professor Wayne Luk is a Professor of Computer Engineering at the Department of Computing, Faculty of Engineering, Imperial College London. He leads the Programming Languages and Systems Section and the Custom Computing Research Group, and directs the EPSRC Centre for Doctoral Training in High-performance Embedded and Distributed Systems and the Centre for Advanced Financial Engineering. He previously served as a Visiting Professor at Stanford University from 2006 to 2009. His research spans FPGA acceleration, quantum computing, deep learning optimization, and algorithm-hardware co-design, with affiliations to the CRUK Convergence Science Centre and the Engineering Secure Software Systems group. His research interests include computational modeling for particle physics, causal discovery in agent-based systems, and high-throughput digital electronics. Notable contributions include FPGA-accelerated algorithms for neural networks, quantum circuit simulation, and Bayesian optimization frameworks. His work emphasizes practical applications of reconfigurable hardware in fields like medical imaging, high-energy physics, and financial systems. Professor Luk is a Fellow of the Royal Academy of Engineering, IEEE, and BCS. His publications focus on advancing hardware-aware machine learning, FPGA-based acceleration techniques, and scalable design methodologies. His research bridges theoretical computer science with applied engineering, addressing challenges in real-time systems, embedded computing, and next-generation computing architectures. His academic leadership includes directing interdisciplinary centers and training programs, fostering collaboration across computing, engineering, and physics. Current projects explore quantum computing tools, causal inference systems, and high-performance graph neural networks for particle physics applications.
Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.
Justine Sherry is the A. Nico Habermann Associate Professor of Computer Science at Carnegie Mellon University, affiliated with the College of Engineering. She holds a PhD (2016) and MS (2012) from UC Berkeley and a BS/BA (2010) from the University of Washington. Her research focuses on networked systems, including middleboxes, cloud computing, congestion control, and hardware acceleration (e.g., SmartNICs/FPGAs). Notable projects include Pigasus (open-source 100Gbps IDS), APLOMB (cloud-based middlebox scaling), and BlindBox (encrypted traffic scanning). Her academic roles include serving on the SIGCOMM CARES Committee, DARPA ISAT Study Group, and ACM CoNEXT Steering Committee. Awards include the Alfred P. Sloan Fellowship, VMware Systems Award, and IETF Applied Networking Prize. She advises over 15 students and collaborates with industry partners like Intel and VMware. Research highlights include radical shifts in datacenter architectures (SmartNIC compute control), fairness in congestion algorithms (BBR analysis), and database-proxy innovations (Tigger with eBPF). Her teaching emphasizes systems as science labs, integrating experimental design and hypothesis testing into projects. Education: PhD UC Berkeley (2016), MS UC Berkeley (2012), BS/BA University of Washington (2010) Labs/Teams: CyLab, SNAP Research Group, CMU Portugal Collaboration Grants: NSF, Intel, Google Faculty Awards
Ozcan Ozturk is a Professor in the Computer Science and Engineering and Electronics Engineering programs at Sabancı University's Faculty of Engineering and Natural Sciences. Previously, he held professorships at Bilkent University and adjunct roles at North Carolina State University. His expertise spans heterogeneous computing, parallel systems, processor architecture, and compiler optimization. He earned his Ph.D. from Penn State University, with prior academic roles at the University of Florida and internships at Intel and Marvell. Education: Ph.D. in Computer Science and Engineering (2007), Pennsylvania State University M.S. in Computer Engineering (2002), University of Florida B.Sc. in Computer Engineering (2000), Bogazici University Research interests include accelerator technologies, GPU-based systems, multicore processors, and compiler optimizations. His work focuses on improving parallelization efficiency, energy optimization, and reliability in heterogeneous architectures. He leads funded projects like 'Machine Learning for Compiler Flags' and 'Graph Accelerator Design'. Notable awards include the Bilkent Teaching Award (2019), BAGEP (2018), and HiPEAC Paper Award (2016). He serves on editorial boards of IEEE and ACM journals and chairs major conferences like ASPLOS and ICS. Grants and collaborations include partnerships with Huawei, Intel, NVIDIA, and TÜBİTAK. He advises over 20 students and has supervised projects in safety-critical systems, FPGA accelerators, and compiler-directed optimizations. His lab develops domain-specific architectures, including RISC-V extensions for graph processing.
Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.
Westley Weimer is a Professor in the Department of Electrical Engineering and Computer Science (EECS) at the University of Michigan, College of Engineering. He teaches advanced courses such as EECS 590 (Advanced Programming Languages) and EECS 481 (Software Engineering), and has previously taught at the University of Virginia. His research integrates software engineering, programming languages, and cognitive science, focusing on automated program repair, program analysis, and the neuroscience of code comprehension. University: University of Michigan School: College of Engineering Department: Department of Electrical Engineering and Computer Science Academic Rank: Professor His research interests include automated program repair (e.g., GenProg), software quality, cognitive modeling of programming, neuroimaging studies of code review, and the application of medical imaging to software engineering. He explores deep questions at the intersection of consciousness, time, and computation, advocating for interdisciplinary approaches to understanding the mind through programming behavior. The most recent publications reflect a trend toward empirical and cognitive studies in software engineering, combining automated repair with human factors, neuroimaging (fMRI, TMS), and real-world software challenges. Themes include bias in code review, programming under cognitive influences, and the neurological basis of code comprehension. His work increasingly bridges computer science with psychology, neuroscience, and social science. Scientific awards include multiple Distinguished Paper Awards at ICSE, FSE, and ESEC/FSE, Best Paper and Runner-up awards, and several 10-Year Most Influential Paper Awards from ASE, GECCO, POPL, and ASPLOS, recognizing the lasting impact of his contributions to automated software repair and program analysis. He has advised numerous PhD and Master’s students, many of whom have gone on to faculty positions or industry research roles. He contributes to academic service through organizing diversity and inclusion initiatives, maintaining graduate career resources, and promoting ethical and inclusive practices in computing. He leads a vibrant research group focused on improving software quality through both technical and human-centered innovations, with ongoing projects in automated repair, cognitive modeling, and secure systems.
Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.
