Lana Josipovic serves as an Assistant Professor within the Department of Information Technology and Electrical Engineering (D-ITET) at ETH Zürich, Switzerland. Her office is located at ETZ G 82, Gloriastrasse 35, 8092 Zürich, with direct contact via +41 44 632 70 61. Her research focuses on sustainable computing and hardware acceleration methodologies, particularly through FPGA implementations and discrete event systems theory. These interests are explicitly reflected in her Autumn Semester 2025 teaching assignments: 227-0085-69L P&S: Let’s make ITET green! (Green IT initiatives) 227-0085-76L P&S: From Software Applications to FPGA Designs 227-0102-00L Discrete Event Systems Her work bridges theoretical control systems with practical sustainability applications in electrical engineering. For collaboration or inquiry, she can be reached at ljosipovic@ethz.ch .
Michela Becchi is an Associate Professor in the Department of Electrical and Computer Engineering at North Carolina State University. She specializes in computer architecture, systems software, and applications, with a focus on heterogeneous systems, parallel algorithms, and acceleration techniques for bioinformatics, pattern recognition, and quantum computing. Her work spans multi-core CPUs, GPUs, FPGAs, and distributed clusters, emphasizing the boundary between hardware and software design. Dr. Becchi holds a Ph.D. and Master’s degree in Computer Engineering from Washington University in St. Louis (2009) and a Bachelor’s degree in Computer Engineering from Politecnico di Milano, Italy (2000). Her research has been recognized with prestigious awards, including the NSF CAREER Award (2015) and the University of Missouri System President Award for Early Career Excellence (2016). Her research interests include compiler and runtime techniques for heterogeneous systems, acceleration of bioinformatics algorithms, and high-speed networking applications. She has pioneered frameworks for efficient data transformation, GPU-accelerated compression, and memory-efficient graph algorithms for quantum computing. Her work also explores thread coarsening, mixed-precision auto-tuning, and secure multi-core processor design. Key contributions include the PILOT runtime system for GPU memory management, the GPU-FPtuner auto-tuner for floating-point applications, and innovative approaches to automata processors for genomic analysis. Her publications emphasize reproducible accuracy in scientific simulations and the optimization of irregular applications on many-core platforms.
Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.
Dr. Ameer Abdelhadi is an Assistant Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on application-specific custom-tailored computer architectures, hardware-efficient deep learning, neurotechnology, and reconfigurable computing. He holds a PhD from the University of British Columbia and has held academic positions at the University of Toronto, Imperial College London, and Simon Fraser University, alongside industry experience in semiconductor design. Education: PhD in Computer Engineering (University of British Columbia, 2016). Research Interests: Hardware acceleration for machine learning and neurotechnology Reconfigurable computing and FPGAs/ASICs Asynchronous circuits and synchronization protocols VLSI physical design and CAD algorithms Publications span high-impact venues such as IEEE Journal of Solid-State Circuits, IEEE Hot Chips, and IEEE Micro. Notable achievements include the 2017 Best Paper Award at ASYNC for work on synchronization FIFOs. Teaching includes COMPENG 4DV4 (VLSI System Design) and ELECENG 4OI6B (Engineering Design). His lab focuses on advancing hardware systems for next-generation applications in AI and biomedical engineering.
Jason Dahlstrom is an Adjunct Assistant Professor of Engineering at Dartmouth College's Thayer School of Engineering and Owner of Web Sensing LLC. His research focuses on embedded systems security, computer architecture optimization, and engineering education innovations. He holds a BS in computer engineering (University of New Hampshire, 2006), MS in biomedical engineering (Dartmouth, 2008), and PhD in embedded system security (Dartmouth, 2015). His work emphasizes cybersecurity for critical infrastructure, particularly in vehicle systems and military communication networks. Key contributions include real-time binary analysis frameworks, FPGA-integrated security monitors, and tactical network interface controllers. He has authored patents related to data security appliances and distributed sensing systems. Recent publications explore vehicle system hardening, cross-domain container security, and hardware-assisted monitoring. His research bridges theoretical computer architecture with practical embedded system implementations, addressing modern threats in connected devices and defense applications.
Michael Ferdman is an Associate Professor in the Department of Computer Science at Stony Brook University, where he leads research in computer architecture and systems. His office is located in Room 343 at Stony Brook, NY 11794-2424, and he can be contacted via phone (631-632-8449) or email. Ferdman directs the Computer Architecture and Systems Laboratory (compas.cs.stonybrook.edu), focusing on next-generation server infrastructure. Ferdman's research spans the entire computing stack with emphasis on: FPGA integration for server environments (Intel HARP, Microsoft Catapult) Machine learning accelerators for convolutional neural networks Server systems optimization in the post-Moore era Network processing and software-defined networking Programming models for emerging memory technologies (HBM, 3D XPoint) Reconfigurable hardware and high-level synthesis His work addresses both performance and security challenges in modern computing infrastructure. Analysis of his 15 most recent publications (2022-2025) reveals consistent focus on: Hardware acceleration techniques (FPGAs, specialized processors) Memory hierarchy optimization and cache management Security vulnerabilities in web applications and systems Post-Moore computing architectures Parallel processing and distributed systems His research shows strong emphasis on practical implementations bridging hardware and software layers. Awards recognizing his contributions include: Graduate Teaching Award (2014) Best Paper Award at ASPLOS XVII Best Paper Finalist at HPCA XVII Three IEEE Micro Top Picks selections (2009, 2012) He teaches advanced courses including CSE 502, CSE 602, and CSE 506 at Stony Brook University.
Patrick Mitran is a full-time Professor at the University of Waterloo's Department of Electrical and Computer Engineering, within the Faculty of Engineering. His research focuses on advanced wireless communication systems, including 5G/6G technologies, millimeter-wave and sub-THz communication, digital predistortion techniques, MIMO systems, and beamforming architectures. He leads projects addressing challenges in transmitter linearization, network resource allocation, and hardware-efficient signal processing. Key research interests include optimizing frequency multiplier-based transmitters, mitigating inter-cell interference in massive MIMO networks, and developing algorithms for reconfigurable intelligent surfaces (RIS). His work often intersects hardware design, signal processing, and network optimization, with applications in next-generation wireless infrastructure. Recent publications highlight innovations in ultrawideband signal generation for 6G testing, practical RIS configurations, and FPGA-based real-time digital predistortion implementations. His contributions emphasize both theoretical advancements and practical system-level solutions. Dr. Mitran's research group collaborates on cutting-edge topics such as hybrid NOMA in multi-cell networks, adaptive coding modulation for Gaussian channels, and interference decoding strategies. His work has been published in top-tier journals and conferences, reflecting a sustained impact on modern wireless communication technologies.
Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.
Jeffrey Krolik is a Professor of Electrical and Computer Engineering at Duke University's Pratt School of Engineering. He holds a Ph.D. in Electrical Engineering from the University of Toronto (1987) and previously served as an Assistant Professor at Concordia University and Assistant Research Scientist at Scripps Institution of Oceanography. Ph.D. University of Toronto (1987) M.A. University of Toronto (1983) B.A. University of Toronto (1980) His research focuses on physics-based and statistical signal processing with applications in radar, sonar, microwave remote sensing, and medical imaging. Key projects include adaptive beamforming for ocean acoustic waveguides, aircraft height finding via HF radar, and motion-robust fMRI algorithms. Recent publications cover multipath mitigation in sonar arrays, vibrational radar backscatter communication, and CNN implementations for radar signal processing. His work spans underwater acoustics, urban radar tracking, and distributed sensor networks. He teaches advanced courses in sensor array signal processing, digital audio systems, and radar applications. His research has been supported through collaborations with institutions like Scripps and consulting roles with ONR, DARPA, and Air Force Rome Laboratories. Key contributions include waveguide invariant processing, matched-field beamforming, and novel approaches to radar clutter suppression in urban and maritime environments. His work integrates statistical signal processing with physical propagation models across diverse domains.
René Jr Landry is a full Professor in the Department of Electrical Engineering at École de technologie supérieure (ETS), Université du Québec, specializing in Global Navigation Satellite Systems (GNSS), avionics, and wireless communication technologies. His academic journey includes a B.Ing. from Polytechnique Montréal, M.Sc. from University of Surrey (UK), and Ph.D. from SupAréo in Toulouse. He maintains active research leadership through two key laboratories: LASSENA (Laboratory of Space Technologies, Embedded Systems, Navigation and Avionics) and LACIME (Communications and Microelectronic Integration Laboratory). His research spans critical aerospace navigation domains including GNSS signal processing, inertial navigation systems, software-defined radio for avionics, radio frequency interference mitigation, and indoor positioning technologies. Landry's work addresses real-world challenges in satellite navigation robustness, precision positioning in urban/denied environments, and next-generation avionic system security. His current projects focus on blockchain-enhanced IoT security, AI-driven GNSS disruption analysis, and adaptive RF front-ends for multi-band avionics applications. Analysis of his recent publications reveals strong emphasis on resilient positioning systems through multi-constellation integration (particularly Iridium-NEXT), blockchain applications for navigation security, and explainable AI techniques for GNSS signal quality assessment. His work increasingly bridges traditional navigation engineering with cutting-edge security and machine learning paradigms. 2014 Prix d'excellence du c.a. pour les services à la collectivité Landry has supervised over 100 graduate students across doctoral, master's, and research projects since 2005, with current supervision extending through Summer 2025. His research funding supports multiple industry partnerships focused on avionics certification, software-defined radio implementations, and next-generation navigation systems. The LASSENA laboratory under his leadership develops certified avionic products from open-source SDR platforms and advances multi-sensor fusion techniques for challenging navigation environments. His research infrastructure includes specialized facilities for GNSS signal simulation, avionics hardware testing, and multi-sensor integration. Current work emphasizes flight-tested validation of RF front-end technologies, blockchain-secured navigation data, and real-time interference mitigation systems for aviation applications.
Luca Carloni is a Professor of Computer Science and Department Chair at Columbia University's Columbia Engineering. He leads the System-Level Design Group, focusing on heterogeneous system-on-chip (SoC) architectures, networks-on-chip (NoC), and embedded systems. Carloni holds a Laurea Summa Cum Laude in Electronics Engineering from the University of Bologna and a PhD in Electrical Engineering and Computer Sciences from UC Berkeley. His work emphasizes specialized hardware design, energy-efficient computing, and FPGA-based prototyping. Research interests include system-level design methodologies for SoCs, embedded accelerators, and quantum computing hardware. He has pioneered frameworks like Embedded Scalable Platforms (ESP) and tools like MosaicSim for rapid SoC prototyping. Carloni has received numerous awards, including the NSF CAREER Award (2006), IEEE Fellow (2017), and multiple best paper awards at DATE and CloudCom conferences. He has served on editorial boards of IEEE Transactions on CAD and ACM Transactions on Embedded Computing , and chaired key conferences like EMSOFT and ESWeek. His research addresses challenges in heterogeneous architectures, power management, and the intersection of machine learning with embedded systems. Current projects explore quantum control systems, brain-computer interfaces, and energy-efficient datacenter computing.
Arrvindh Shriraman is an Associate Professor and Program Director of Software Systems at Simon Fraser University's School of Computing Science in Surrey. His research focuses on energy-efficient software, multicore memory systems, and optimizing hardware/software interfaces for parallel programming. He holds a Ph.D. (2010) and M.S. (2006) in Computer Science from the University of Rochester, and a B.Eng. (2004) from the University of Madras. He teaches courses on parallel programming and energy-conscious software design. His research interests include synchronization mechanisms for domain-specific architectures, cache optimization, and FPGA-based acceleration. He has contributed to frameworks like Mu-grind for HLS-generated RTL instrumentation and TAPAS for parallel accelerator generation. Notable projects include RANGE-BLOCKS for synchronization in domain-specific systems and TapeFlow for gradient computation in neural networks. His work emphasizes real-time verification of autonomous systems and safety-critical trajectory planning for underwater vehicles. Shriraman collaborates closely with the Tangent Lab, exploring cutting-edge solutions in hardware-software co-design and embedded systems. His teaching and research bridge theoretical computer science with applied engineering challenges, addressing scalability, efficiency, and safety in modern computing systems.
Lin Zhong is the Joseph C. Tsai Professor of Computer Science at Yale University, leading the Efficient Computing Lab. He holds a Ph.D. from Princeton University and M.S./B.S. degrees from Tsinghua University. Previously, he served at Rice University from 2005 to 2019. His research focuses on optimizing computing efficiency, quantum error correction, operating systems, and mobile systems. Education: Ph.D., Princeton University M.S., Tsinghua University B.S., Tsinghua University Research Interests: His work spans quantum computing (e.g., decoding algorithms for surface codes), operating systems (safety, correctness, and lightweight kernels), and mobile/networking systems (massive MIMO, energy-efficient designs). Recent trends include integrating large language models (LLMs) into robotics and securing cloud-based AI workflows. Awards: NSF CAREER Award ACM SIGMOBILE RockStar (2014) and Test of Time (2022) Fellowships from IEEE and ACM Best Paper Awards at ACM MobileHCI, IEEE PerCom, ACM MobiSys, and more Lab & Teams: His Efficient Computing Lab explores systems for quantum error correction (e.g., FPGA-based decoders), secure embedded systems, and LLM-driven robotics. Projects include TimelyLLM (real-time LLM serving) and Blindfold (confidential memory management).
Professor David Thomas holds the position of Professor in Computer Engineering at the University of Southampton's Electronics and Computer Science Department. His research focuses on the intersection of software and hardware, particularly leveraging FPGAs for novel digital architectures and event-driven computing. He has a notable academic trajectory, having previously served as a Lecturer and Senior Lecturer at Imperial College London before joining Southampton in 2021. Dr. Thomas is actively involved in supervising PhD students and contributes to interdisciplinary research projects funded by the EPSRC, such as the SONNETS initiative exploring scalable event-triggered systems. Education: BSc in Computer Science (Imperial College London), PhD in Digital Architectures (Imperial College London). Postdoctoral roles included Research Associate and Research Fellow at Imperial's Department of Computing. Research Interests: Event-driven computing, FPGA-based systems, high-level synthesis, and high-performance computing. His work emphasizes practical implementations of theoretical models, such as custom processors and application-specific accelerators. Current projects include optimizing random number generation for FPGAs and exploring meta-programming techniques for hardware design. Advising and Grants: Supervises multiple PhD students in areas like neuromorphic computing and algorithm optimization. Active in securing funding for distributed system architectures and FPGA-based solutions. Labs/Teams: Member of the Cyber Physical Systems research group. Collaborates with interdisciplinary teams on projects like POETS (Partially Ordered Event-Triggered Systems) for large-scale parallel computing.
Russell Tessier is a Professor and Department Head of Electrical and Computer Engineering at the University of Massachusetts Amherst, affiliated with the Manning College of Information and Computer Sciences. His research focuses on reconfigurable computing, FPGA architectures, and hardware security, with notable contributions in CAD algorithms for FPGAs, embedded systems, and multi-tenant FPGA vulnerability analysis. Education: B.S.C.S.E., Rensselaer Polytechnic Institute (1989) M.S. and Ph.D., Massachusetts Institute of Technology (1992 and 1999) Research Interests: Dr. Tessier's work spans FPGA security (e.g., side-channel attacks, power distribution vulnerabilities), reconfigurable cloud computing, and hardware acceleration for applications like SAR imaging and machine learning. His lab, the Reconfigurable Computing Group, develops open-source FPGA cores (e.g., FlexGrip GPGPU, DE4 NetFPGA) and explores cutting-edge security countermeasures. Awards and Honors: Chancellor's Leadership Fellow (2015-2016) NSF Information Technology Research Grant Lilly Teaching Fellow (2002-2003) Multiple College of Engineering Excellence Awards Grants and Projects: Active funding includes NSF SaTC grants on reconfigurable cloud security and NASA support for snowpack measurement systems. His research also addresses FPGA-based solutions for cybersecurity, such as intrusion detection and power-side channel mitigation. Labs and Teams: Leads the UMass Reconfigurable Computing Group, which collaborates on open-source FPGA tools, security frameworks, and embedded system designs. The group maintains platforms like the DE4 NetFPGA and FlexGrip architecture.
