Find Academic Supervisors

• High-Level Synthesis
• FPGA Design
• Hardware Engineering
• +3 more

Sakari Lahti is a Lecturer in the Department of Computing Sciences at Tampere University, within the Faculty of Information Technology and Communication Sciences. His primary responsibilities include teaching digital logic and hardware design. He holds an ORCID identifier: 0000-0002-9915-4784 . Lahti's research focuses on High-Level Synthesis (HLS) for FPGAs, with emphasis on optimizing embedded systems, real-time applications, and digital signal processing. His work spans FPGA implementation techniques, compiler optimizations for HLS tools, and practical applications in media processing and wireless communications. Notable projects include real-time HEVC video encoding and nonlinear self-interference cancellation systems. His publications reflect a sustained contribution to FPGA-based hardware design, with a decade of work from embedded systems (2002) to modern C++ integration in HLS (2023). Collaborations include colleagues like Teemu Hämäläinen and Jari Vanne, focusing on bridging software and hardware design methodologies. His research also extends to educational aspects, such as real-world product development in system design courses. Lahti’s work is peer-reviewed and published in prestigious venues like IEEE Transactions and conferences like DDECS and ISCAS. His research unit is the Unit of Computing Sciences at Tampere University.

• Computer Security
• 5G Networks
• Privacy Preservation
• +6 more

Philip Ginzboorg is a Professor of Practice at the Department of Computer Science, Aalto University. His research focuses on advanced security and privacy challenges in modern networking systems, with a particular emphasis on 5G, edge computing, and disruption-tolerant networks. His recent work explores AKMA (Authentication and Key Management for Access) protocols for secure mobility in 5G edge computing environments, privacy-preserving authentication mechanisms , and fragmentation algorithms for disrupted links . Collaborations with Valtteri Niemi, Jörg Ott, and other researchers highlight his interdisciplinary approach. Key publication trends span 5G security , privacy in pervasive networks , DTN (Disruption-Tolerant Networking) , and cryptographic protocols for constrained systems . Notable contributions include defenses against downgrade attacks on identity privacy and novel approaches to IMSI-based routing.

• System-on-Chip (SoC) Design
• FPGA-Based High-Level Synthesis
• Real-Time Embedded Systems
• +5 more

Timo Hämäläinen is a Professor of Computer Engineering at Tampere University, leading the Unit of Computing Sciences within the Faculty of Information Technology and Communication Sciences. He is a core member of the System-on-Chip research group and the Computer Engineering Team, actively contributing to the System-on-Chip Hub initiative. His research focuses on System-on-Chip (SoC) design methodologies, FPGA-based high-level synthesis, real-time embedded systems, and open-source hardware-software co-design frameworks like RISC-V and HEVC encoding. He has pioneered work on agile SoC development processes and validation techniques for large-scale hardware systems. Key research areas include: High-level synthesis (HLS) optimization for FPGAs Real-time processor architectures and context-switching latency reduction Formal verification of IP-XACT-compliant SoC designs Resilient RISC-V MPSoC implementations Hardware-accelerated algorithms for signal processing and networking His recent publications (2023-2025) emphasize agile SoC development frameworks, hardware-software co-design for real-time systems, and validation methodologies for large-scale embedded systems. He has contributed to open-source projects like Kvazaar HEVC encoder and the Kactus2 IP-XACT toolchain. Academic advising includes students such as Santéri Mäki-Äijö (formal verification), Arto Oinonen (RISC-V tooling), and Sakari Lahti (processor modeling). His work integrates academic research with industrial collaboration through frameworks like the Fault-slip-Through quality assessment methodology.

• Communications Engineering
• Positioning Technologies (GNSS)
• Embedded Processor Systems
• +4 more

Jari Nurmi is a Full Professor at Tampere University's Faculty of Information Technology and Communication Sciences, Department of Electrical Engineering. With over 30 years of experience in academia and industry, he specializes in communications engineering, positioning technologies, embedded systems, and reconfigurable computing. His roles include Director of the national DELTA doctoral training network, head of the European Joint Doctorate A-WEAR program, and coordinator of APROPOS MSCA ITN. He has supervised 32 PhD dissertations and over 160 MSc theses. His research focuses on embedded processor systems, reconfigurable computing, approximate computing, and positioning technologies (especially GNSS receiver architectures). He is actively involved in organizing international conferences like IEEE Nordic Circuits and Systems Conference and serves on editorial boards of three journals. His recent work includes advancements in neural network inference on FPGAs, 5G NR localization, and energy-efficient edge AI for autonomous systems. Nurmi has been recognized for his contributions to conference organization and innovation. His publications span topics such as FPGA optimization, GNSS error modeling, and machine learning for healthcare applications. He leads initiatives like the EWOk dataset compression framework and the Hard SyDR benchmarking environment for GNSS algorithms.

• Robot Learning
• Object-Centric Learning
• Machine Learning
• +3 more

Vivienne Huiling Wang is a Postdoctoral Researcher at Aalto University's Department of Electrical Engineering and Automation, specializing in Machine Learning and Robotics. Her research focuses on object-centric learning, hierarchical reinforcement learning, and probabilistic modeling for robotic systems. Robot Learning Object-Centric Learning Probabilistic Subgoal Representations Her recent work (2023-2025) spans object representation techniques, adversarial subgoal generation, and processor performance estimation using machine learning. She contributes to the Robot Learning research group and collaborates with experts in computer vision and AI planning. Current affiliations: Aalto University Department of Electrical Engineering and Automation

• Cryptography
• Hardware Security
• Embedded Systems
• +2 more

Kimmo Järvinen serves as a Visiting Professor in the Department of Electronics and Nanoengineering at Aalto University, actively contributing to the Adjunct Professor Asokan N. research group. His institutional affiliation centers on advancing cryptographic solutions for modern security challenges within the university's engineering ecosystem. His research spans cutting-edge cryptography with emphases on hardware security, embedded systems protection, and efficient algorithm design. Järvinen specializes in elliptic curve cryptography implementations, side-channel attack countermeasures, and hardware acceleration techniques for resource-constrained environments like IoT devices. His work bridges theoretical cryptographic constructs with practical hardware deployment, prioritizing both security robustness and computational efficiency in real-world applications. Analysis of his 2014-2018 publications reveals consistent innovation in finite field arithmetic optimization, scalar multiplication efficiency, and physical attack resistance. His research trajectory demonstrates increasing focus on IoT security integration, with significant contributions to FPGA-based cryptographic accelerators and lightweight implementations for constrained devices. Key thematic threads include endomorphism exploitation for performance gains, binary field operation optimization, and protocol-level privacy enhancements for mobile networks. Dr. Järvinen operates within Adjunct Professor Asokan's cybersecurity research collective, which explores hardware-software co-design approaches to cryptographic system vulnerabilities. This team environment fosters cross-disciplinary collaboration on securing next-generation communication infrastructures and embedded platforms.

• Computer Engineering
• Network-on-Chip (NoC)
• Fault-Tolerant Systems
• +3 more

Heikki Kariniemi is a Doctoral Researcher at the Faculty of Engineering and Natural Sciences (Tampere University). His work focuses on advanced computer architecture and fault-tolerant systems. Tampere University Research Interests: Network-on-Chip (NoC) design Fault-tolerant communication protocols Multiprocessor Systems-on-Chip (MPSoC) Field-Programmable Gate Arrays (FPGA) Globally Asynchronous Locally Synchronous (GALS) architectures Publication Trends (2001-2010): 21 total outputs, including 18 conference papers and 1 dissertation. Key themes: reconfigurable multiprocessor systems, fat-tree network topologies, and FPGA-based fault-tolerant communication mechanisms. Academic Activities: Session chair at SoC 2009 and SoC 2010 symposia Peer reviewer for journals: IEEE Transactions on Circuits and Systems, IEEE Transactions on Electronic Publishing Referee for conference articles at NORCHIP 2009

• Machine Learning
• Robotics
• Autonomous Driving
• +3 more

Jatan Shrestha is a Doctoral Researcher at Aalto University, affiliated with the Department of Electrical Engineering and Automation. His research focuses on applying machine learning techniques to solve complex problems in robotics and autonomous systems. Department: Electrical Engineering and Automation Email: jatan.shrestha@aalto.fi Research Interests: Jatan's work spans machine learning, robotics, and optimization. Key areas include autonomous driving algorithms, multi-agent trajectory planning, visibility-aware navigation, and GPU-accelerated computing for real-time robotic applications. Publication Trends: His research output demonstrates expertise in applying machine learning to hardware optimization (2024), advancing autonomous driving algorithms in dense traffic scenarios (2023), and developing GPU-based optimization frameworks for robotic navigation (2021-2022).

Arianne MeijerView profile

Researcher

• Quantum Computing
• Quantum Software Engineering
• Quantum Algorithms
• +3 more

Arianne Meijer is a Postdoctoral Researcher in the Department of Computer Science at the University of Helsinki and serves as a Quantum Software Engineer at IQM Germany GmbH since September 2024. Her research focuses on quantum computing, particularly quantum software engineering, compilation, and algorithm optimization for NISQ devices. She has contributed to advancements in stabilizer circuits, Pauli string decompositions, and hybrid quantum-classical systems. Institution: University of Helsinki Department: Computer Science Industry Role: Quantum Software Engineer (IQM Germany GmbH) Collaborations: Finnish Quantum Flagship, QuantumWare Her research output spans quantum compilation, algorithm design, and hardware-software integration. Projects like EM4QS and Finnish Quantum Flagship highlight her work in quantum middleware and device benchmarking. She has published extensively on topics such as barren plateaus, variational quantum regression, and architecture-aware synthesis. Notably, her 2024 work critiqued the practicality of quantum circuit models and explored quantum string matching for graphs. Meijer's recent activities include external teaching on quantum software, and her collaborations extend across Finland and Germany. Her work emphasizes practical solutions for quantum software stack limitations and optimizing compilation processes for current hardware constraints.