Caroline Trippel is an Assistant Professor in the Departments of Computer Science and Electrical Engineering at Stanford University. Her research focuses on ensuring correctness and security in computer systems through formal methods, with particular emphasis on hardware verification, memory consistency models, and mitigating vulnerabilities like Spectre/Meltdown. She previously worked at Facebook’s FAIR SysML group before joining Stanford. Education: PhD in Computer Science, Princeton University BS in Computer Engineering, Purdue University Her work has influenced the RISC-V ISA memory consistency model and produced tools like CheckMate, which automatically synthesizes hardware exploits for security verification. She explores privacy-preserving ML, ML-driven hardware optimizations (e.g., neural recommendation), and datacenter reliability. Her research has earned awards including the 2020 ACM SIGARCH Dissertation Award and NVIDIA Fellowship. Key contributions include: Formal analysis of RISC-V memory models Exploitation synthesis frameworks (CheckMate) Hardware-software contracts for security Defenses against microarchitectural side-channel attacks Current projects include: VeriCoder: LLM-enhanced RTL code verification Multi-μPATH synthesis for security validation Near-data processing (RecSSD) for recommendation systems
Jeyavijayan 'JV' Rajendran is an Associate Professor in the Department of Electrical and Computer Engineering at Texas A&M University, part of the College of Engineering. He is an ASCEND Fellow and leads the Secure and Trustworthy Hardware (SETH) Lab. His research focuses on hardware security, computer security, and novel applications of AI in secure hardware design. Education: PhD in Electrical Engineering (NYU 2015), MS in Computer Engineering (NYU Tandon 2010), BE in Electronics and Communication Engineering (Anna University 2008). Research Interests: Hardware Security, Computer Security, Logic Locking, Hardware IP Protection, and Reinforcement Learning for Security. He explores AI-driven approaches to detect vulnerabilities, protect intellectual property, and enhance secure hardware design through fuzzing, obfuscation, and formal verification. Notable Awards: 2022 Office of Naval Research Young Investigator Award, 2021 IEEE CEDA Ernest Kuh Early Career Award, 2017 NSF CAREER Award. Lab and Teams: The SETH Lab focuses on trustworthy hardware design, developing techniques to secure integrated circuits against reverse engineering and IP theft. Current projects include LLM-based hardware code generation, formal approaches for hardware fuzzing, and AI-driven vulnerability detection.
Maria Mushtaq is an Associate Professor at Telecom Paris , affiliated with the Information Processing and Communication Laboratory (LTCI) and the Secure and Safe Hardware (SSH) Lab . She received her PhD in Information Security from the University of South Brittany, France (2019) and completed 2 years of postdoctoral research at LIRMM, University of Montpellier under the CNRS excellence post-doc grant. Research Focus: Microarchitectural vulnerability assessment, runtime mitigation against side/covert-channel attacks, cryptanalysis, OS-based security primitives, and hardware-software interface security Technical Expertise: Cache timing attacks, transient execution attacks (Spectre/Meltdown), Hardware Performance Counter analysis, gem5 simulation Her recent work involves RISC-V security analysis using gem5 simulations and machine learning for attack detection. She serves as Guest Editor for the Journal of Applied Sciences special issue on Side Channel Attacks in Embedded Systems and has been on the Program Committee for the European Test Symposium (2020-2021). 2021 HiPEAC Collaboration Grant recipient Organized IP Paris Winter School on Microarchitectural Security (2022) Active in international conferences as panelist and keynote speaker
Prof. Tim Güneysu is a full Professor and Head of the Security Engineering department at the Faculty of Computer Science, Ruhr-Universität Bochum. He serves as Vice Dean for Strategy and Finances (since 2023) and previously as Speaker of the Horst-Görtz Institute for IT-Security (2020-2023). His academic journey includes roles as Associate Professor at the University of Bremen (2015-2017) and Assistant Professor at Ruhr-Universität Bochum (2011-2015). He also holds positions at the German Research Center for Artificial Intelligence (DFKI) and has conducted postdoctoral research at UMass Amherst. His research focuses on Security-by-Design principles, CAD for Security, and countermeasures against physical attacks. He emphasizes efficient cryptographic implementations and system-level hardware security. Key areas include post-quantum cryptography, side-channel resistant designs, and secure embedded systems. He has contributed over 200 publications in top venues, with recent work on FPGA-based cryptographic accelerators, secure hardware extensions (e.g., KeyVisor), and post-quantum algorithms for IoT. His research themes include agile signature acceleration, fault attack mitigation, and hardware-software co-design for security. Notable projects include CONVOLVE (edge-AI security) and QuantumRISC (quantum-safe systems). His work bridges theoretical cryptography with practical hardware implementations, emphasizing real-world security applications.
Fan Yao is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Central Florida's College of Engineering and Computer Science. She received her Ph.D. in Computer Engineering from The George Washington University in 2018 and currently leads the Computer Architecture and Systems Research (CASR) lab. Her research focuses on the intersection of computer architecture, security, and machine learning, with particular emphasis on hardware-based security vulnerabilities and defenses. Dr. Yao's research interests span computer architecture, hardware and system security, AI security, energy-efficient computing, and cloud computing. Her work addresses critical security challenges in modern computing systems, particularly focusing on microarchitecture attacks, hardware-based model tampering in deep learning systems, and information leakage threats in emerging non-volatile memory systems. She has developed innovative defense mechanisms against cache timing channels, branch predictor vulnerabilities, and GPU-based side channels. Her recent publications demonstrate a strong focus on AI security (particularly Deep Neural Network vulnerabilities), hardware security (including cache and branch predictor attacks), and secure memory architectures. The research shows an evolution from traditional computer architecture topics toward the security implications of AI hardware and emerging memory technologies, with increasing emphasis on practical attacks and defenses in real-world systems. NSF GW I-Corps Site Grant Award, 2018 Best Dissertation Award, GWU, 2018 The Norris & Betty Hekimian Engineering Endowment Fellowship, GWU, 2017 Top Picks in Hardware and Embedded Security, 2019 NSF CAREER project award, 2024 Dr. Yao currently leads multiple NSF-funded research projects including 'Understanding and Taming Deterministic Model Bit Flip Attacks in Deep Neural Networks' (NSF SaTC, 2020-2023), 'Towards Secure-By-Design Integration of Emerging Non-Volatile Memory in Future System' (NSF CNS, 2020-2023), and 'Architecting Secure-by-Design Memristor-Based Memories' (NSF CNS, 2019-2022). She has successfully mentored numerous PhD students, many of whom appear as first authors on top-tier conference publications, demonstrating her commitment to graduate education and research mentorship. As the leader of the CASR lab, Dr. Yao oversees a vibrant research group focused on building secure-by-design, efficient, and advanced future systems through novel techniques spanning hardware, computer architecture, and systems. The lab actively publishes at top computer architecture and security conferences including ISCA, MICRO, HPCA, IEEE S&P, and USENIX Security, with multiple papers accepted to these venues annually. The group has developed several influential tools and frameworks for security analysis, including proof-of-concept code for BranchSpec exploits that has been widely cited in the hardware security community.
University of North Carolina at Chapel HillUnited States
Andrew Kwong is an Assistant Professor in the Department of Computer Science at the University of North Carolina at Chapel Hill, specializing in computer security and applied cryptography with a focus on side-channel attacks and defenses. His research bridges hardware vulnerabilities and cryptographic systems, particularly targeting microarchitectural weaknesses. His primary research interests include Rowhammer-based exploits , side-channel attacks on cryptographic implementations , hardware security modules , and microarchitectural vulnerabilities . Kwong investigates how physical hardware properties (e.g., DRAM disturbance errors, cache hierarchies, acoustic properties) can compromise system security, with recent work demonstrating end-to-end key recovery against post-quantum cryptography and novel Rowhammer amplification techniques. His publication record features high-impact venues including IEEE S&P (5 papers), USENIX Security (4 papers), and CCS (2 papers), with notable work When Frodo Flips receiving a Best Paper Award Honorable Mention at CCS 2022. Research trends show consistent focus on practical hardware-assisted attacks, evolving from acoustic side-channels (2018-2019) to Rowhammer sophistication (2020-2025). Best Paper Award Honorable Mention (CCS 2022) Kwong teaches graduate courses including Hardware Security and Side-Channels (COMP 790-184) and Research Topics in Computer Security (COMP 790-185), emphasizing hands-on lab assignments for conducting and defending against hardware attacks. His syllabi cover foundational topics like cache side-channels, Spectre variants, Rowhammer, and trusted execution environments, requiring students to implement real-world attacks through programming assignments.
Georgios Portokalidis is an Associate Research Professor at IMDEA Software Institute and Visiting Research Professor at Stevens Institute of Technology. He leads research in software systems security with focus on binary analysis, software hardening, and operating system security. His research develops practical defenses against software vulnerabilities through techniques like binary debloating, system call filtering, and hardware-assisted security. Current projects explore Rust language security, processor-assisted protection mechanisms, and vulnerability mitigation through code reduction. Publication trends show evolution from foundational binary analysis to applied security hardening, with recent emphasis on Rust security, hardware-assisted defenses, and real-world system protection. Work demonstrates consistent focus on practical, deployable security solutions. He has supervised numerous PhD students and postdocs, currently mentoring researchers at IMDEA. His group investigates binary analysis, software debloating, and system hardening techniques. Major grants include DARPA YFA (2021-2023) and ONR funding (2017-2022) supporting adaptive binary debloating research. Leads the systems security research group at IMDEA Software Institute, collaborating with international partners. Maintains active research partnerships and regularly contributes to top security conferences as program committee member.
Setareh Rafatirad is an Assistant Professor in the Department of Electrical and Computer Engineering at George Mason University's College of Engineering and Computing. Her research spans hardware security, machine learning for security applications, and IoT security systems. Her research interests focus on hardware security, machine learning for security applications, IoT security, side-channel attacks, and malware detection. She has developed innovative approaches for securing integrated circuits, detecting malware using machine learning techniques, and protecting against side-channel vulnerabilities in computer systems. Her work bridges the gap between hardware design and security, creating practical solutions for emerging security challenges in computing systems. Her recent publications demonstrate a strong trend toward applying machine learning techniques to security problems, particularly in hardware and embedded systems. She has made significant contributions to understanding and mitigating side-channel attacks, developing secure machine learning models, and creating efficient security solutions for resource-constrained devices. Her work shows increasing interdisciplinary reach, connecting hardware security with healthcare applications and educational technologies. Dr. Rafatirad has collaborated extensively with researchers including Houman Homayoun, Avesta Sasan, and Sai Manoj P. Dinakarrao. She has secured research funding for projects related to hardware security and machine learning applications, though specific grant details are not provided in the available information.
Marco Guarnieri is an Associate Professor at IMDEA Software Institute in Madrid, Spain. His research focuses on the design, analysis, and implementation of practical systems for securely storing and processing sensitive data, with particular emphasis on security at the hardware-software boundary and microarchitectural attacks and defenses. Guarnieri received his PhD in Computer Science in 2017 from ETH Zurich's Institute of Information Security, following an MSc (2012) and BSc (2010) in Computer Engineering from Università degli Studi di Bergamo. His research spans security and privacy, program verification, programming languages, and formal methods. Guarnieri's work has particularly focused on addressing vulnerabilities related to speculative execution (Spectre attacks), side-channel analysis, hardware-software security interfaces, and leakage contracts. His approach often combines formal verification techniques with practical system implementation to develop robust security solutions. Guarnieri's publications reveal a strong focus on microarchitectural security, with recent work addressing secure speculation countermeasures, compiler security guarantees against Spectre attacks, side-channel security of cryptographic implementations, and hardware-software leakage contracts. His research shows a progression from database security early in his career to the hardware-software security boundary that characterizes his current work. Among his notable achievements are a Best Paper Award at CCS 2024 and Distinguished Paper Awards at CCS 2023 and CCS 2022. His paper 'Hardware-Software Contracts for Secure Speculation' also received a Best Paper Award. Guarnieri actively contributes to the academic community through program committee roles, including the PriSC Steering Committee, and has organized events such as PLMW@PLDI 2023. He is seeking talented researchers (interns, PhD students, and postdocs) to join his group at IMDEA Software Institute to work on security at the hardware-software interface.
Dr. Michael Schwarz is a tenured faculty member at the CISPA Helmholtz Center for Information Security in Saarbrücken, Germany, where he leads the RootSec research group. Since 2020 he has been investigating microarchitectural side-channel attacks, system security, CPU security, transient-execution vulnerabilities, and corresponding defense mechanisms. He previously served as a post-doctoral researcher (2019–2020) and PhD student (2016–2019) at Graz University of Technology, after earning two master’s degrees in computer science and software engineering with a security focus. Education PhD, Graz University of Technology, 2019 — “Software-based Side-Channel Attacks and Defenses in Restricted Environments” (Advisor: Daniel Gruss) MSc, Computer Science, Graz University of Technology MSc, Software Engineering, Graz University of Technology Research Interests Dr. Schwarz’s work centers on microarchitectural side-channel attacks and system security , spanning: CPU security and transient-execution vulnerabilities (Meltdown, Spectre, Fallout, LVI, ZombieLoad, ÆPIC Leak, CacheWarp) Detection, mitigation, and formal guarantees against microarchitectural leakage Hardware–software co-design for secure operating systems and trusted execution environments Reverse engineering of CPU internals, cache architectures, and prefetchers Browser and web-platform security, including sandbox bypasses and fingerprinting Compiler security and constant-time programming enforcement Scientific Awards & Recognition 2022 Busy Beaver Award for “Foundations of Cybersecurity II” 2021 Busy Beaver Award for “Side-Channel Attacks and Defenses” 2020 EuroSys Roger Needham PhD Award 2019 IEEE S&P Distinguished Paper Award (Spectre) 2019 NSA Best Scientific Cybersecurity Paper Competition Honorable Mention (Meltdown) 2019 Open Exploit Award (Meltdown & Spectre) 2018 CSAW Best Paper Award (Meltdown) 2018 Pwnie Awards: Best Privilege Escalation Bug & Most Innovative Research 2023 USENIX Security Noteworthy Reviewer Award 2023 WOOT Best Paper Award (CustomProcessingUnit) 2022 Pwnie Award for Best Desktop Bug (ÆPIC) 2022 AI 2000 Security & Privacy Honorable Mention 2021 CCSW Best Paper Award & CSAW Best Paper 3rd Place Advising & Collaborations Dr. Schwarz currently mentors numerous PhD students and post-docs within the RootSec group. His collaborations extend across CISPA, Graz University of Technology, and an international network visible through extensive multi-author publications at top-tier venues including USENIX Security, IEEE S&P, ACM CCS, NDSS, ESORICS, DIMVA, ASPLOS, WWW, FC, and specialized microarchitecture security conferences. Labs & Teams He heads the RootSec Research Group at CISPA, whose core mission is to uncover, analyze, and mitigate microarchitectural and system-level security threats. The group maintains close links with industry partners, open-source communities, and policy makers to ensure that research findings are rapidly translated into practical defenses deployed in modern operating systems and processors.
Mohammadkazem Taram is an Assistant Professor in the Department of Computer Science at Purdue University, joining in Fall 2022. He holds a PhD from the University of California San Diego (UCSD), completed in 2022. His research focuses on computer architecture and computer security, particularly microarchitectural attacks, performance mitigations, and security-enhanced hardware design. He has been awarded the ACM SIGMICRO Dissertation Award for his doctoral work and has received several best paper awards for his publications in top-tier conferences like ASPLOS and ISCA. His research interests include hardware security vulnerabilities, secure execution environments, and optimizing performance-security trade-offs. Notable contributions include work on Extended User Interrupts (xUI) , Pathfinder control-flow attacks, and Hardware-Assisted Fault Isolation (HFI) . He actively collaborates with industry and academia, evidenced by his roles in developing novel mitigation techniques against speculative execution and side-channel attacks. Teaching: CS-426 (Computer Security), CS-593 (Microarchitecture Security), and CS-593 (Principles in Computer Architecture) at Purdue. Students: Advises Milad Esrafilian Najafabadi, Berk Aydogmus, and others, with co-advisory roles on Qi Ling and Gustavo Franco Camilo. Labs/Teams: Leads a research group focusing on hardware security and architecture, with a focus on practical and scalable defenses. Publications span top venues like ASPLOS, ISCA, and USENIX Security, with artifacts and open-source contributions. His work emphasizes bridging the gap between theoretical security concepts and real-world hardware implementations.
Marco Vassena is an Assistant Professor in the Department of Information and Computing Sciences at Utrecht University, Netherlands. His research bridges Programming Languages and Security, developing principled methods to build systems with reliable security guarantees through language-based techniques. Previously, he served as a visiting assistant professor at Stanford University and as a postdoctoral researcher at CISPA Helmholtz Center for Information Security, where he co-founded the CISPA-Stanford Center for Cybersecurity. Education PhD in Computer Science, Chalmers University of Technology (supervised by Alejandro Russo) Dr. Vassena specializes in language-based security, with core expertise in memory safety (particularly for WebAssembly via his MSWasm framework), constant-time programming for cryptographic code, information flow control, and defenses against microarchitectural attacks like Spectre. His work applies type systems, compilers, program analysis, and formal verification to create practical security solutions for real-world systems, often targeting low-level vulnerabilities in hardware and software interactions. Analysis of his 15 most recent publications reveals a clear evolution: starting with foundational work on information flow control for concurrent and lazy programs (2016-2019), progressing to memory safety for WebAssembly (2019-2023), and culminating in robust constant-time cryptography (2021-2025). A consistent theme is addressing hardware-level vulnerabilities through compiler and language techniques, with increasing focus on practical implementations for WebAssembly and cryptographic systems. Scientific Awards Veni grant (2023) - Prestigious Dutch Research Council award for early-career researchers Dr. Vassena actively mentors future researchers through Utrecht University's PhD program, currently advertising open positions for candidates interested in applying compilers and program analysis to security challenges. His Veni grant funds these efforts while supporting his research on verified security techniques. He contributes extensively to the academic community as program committee member for POPL, PLDI, and PriSC conferences, and has organized workshops including PLMW@PLDI and PriSC sessions. His collaborations span institutions like CISPA Helmholtz Center and Stanford University, often focusing on WebAssembly security and microarchitectural attack defenses.
Dmitry Evtyushkin is an Associate Professor in the Department of Computer Science at William & Mary. He holds a Ph.D. in Computer Science from Binghamton University, advised by Prof. Dmitry Ponomarev (Binghamton) and Prof. Nael Abu-Ghazaleh (UC Riverside). His research focuses on microarchitecture security, including side/covert channels, isolated execution mechanisms, and secure hardware design. He is particularly known for pioneering work on 'microarchitectural weird machines' to explore hidden CPU vulnerabilities and developing defenses against branch predictor exploits. His research is supported by grants such as the NSF CAREER Award (2022), Coastal Virginia Center for Cyber Innovation (2022), and Intel Side Channel Academic Programme (2018-21). Current projects include secure branch predictor designs, mitigating transient execution attacks, and uncovering novel vulnerabilities in CPU interconnects and memory controllers. Education: Ph.D. in Computer Science, Binghamton University Grants: NSF CAREER, NSF CRII, Intel SCAP, Qualcomm gifts Labs/Teams: Research group at William & Mary focusing on hardware security His work bridges microarchitecture and cybersecurity, aiming to enhance system security without compromising performance.
Max Planck Institute for Security and PrivacyGermany
Peter Schwabe is a scientific director at the Max Planck Institute for Security and Privacy (MPI-SP) and a part-time professor in the Digital Security Group at Radboud University, Nijmegen, The Netherlands. His primary research focuses on cryptographic engineering, particularly post-quantum cryptography, secure cryptographic implementations, and high-assurance systems. He holds a PhD from Eindhoven University of Technology (2011) and a Diplom in Computer Science from RWTH Aachen University (2006). His work includes leading projects like the ERC-funded EPOQUE project, which engineered post-quantum cryptographic standards. He contributed to NIST’s post-quantum cryptography standardization efforts, notably as a core developer of CRYSTALS-Kyber and CRYSTALS-Dilithium. His research spans lattice-based cryptography, code-based cryptography, and formal verification of cryptographic software. Publications highlight advancements in secure implementations against side-channel and speculative execution attacks, high-assurance cryptographic libraries (e.g., EasyCrypt), and practical post-quantum TLS protocols. Key contributions include optimizing cryptographic algorithms for embedded systems (ARM Cortex-M) and formal verification of KEMs like ML-KEM. Scientific awards include an ERC Starting Grant (2018). He advises numerous PhD students and collaborates with industry and academia on cryptographic standards and security. His labs focus on cryptographic engineering, with teams advancing both theoretical and applied aspects of post-quantum security.
Marco Vassena is an Assistant Professor at the Department of Information and Computing Sciences, Utrecht University. His research focuses on using programming language techniques like type systems, compilers, and program verification to build secure systems with reliable security guarantees. Affiliation: Utrecht University, Netherlands Research Areas: Language-based security, memory safety, constant-time programming, information flow control, WebAssembly security, and defenses against microarchitectural attacks. His work includes developing frameworks for secure execution environments, such as MSWasm for WebAssembly, and advancing tools like Blade to mitigate speculative leaks in cryptographic code. He has contributed to leading conferences including POPL, PriSC, and PLDI. Scientific Awards: Veni Grant (2023)
