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Xiaokang QiuView profile

Associate Professor

• Programming Languages
• Software Engineering
• Program Verification
• +2 more

Xiaokang Qiu is an Associate Professor at Purdue University's Elmore Family School of Electrical and Computer Engineering. His work bridges theoretical and applied research in programming languages and software engineering. Current Role: Associate Professor at Purdue University Research Focus: Program verification, synthesis, and automated deduction Over the past decade, Xiaokang's research has centered on advancing program synthesis techniques. His work appears in leading venues like POPL, PLDI, and SAS, where he explores: Syntax-guided synthesis for bit-vector operations Concurrent string transformation synthesis Library-based synthesis frameworks Recursive program verification He actively contributes to the academic community as a committee member and session chair at conferences including POPL, VMCAI, and SPLASH. His research addresses fundamental challenges in automating code generation while ensuring formal correctness.

Bradford L. ChamberlainView profile

Adjunct Professor

• Parallel Computing
• Programming Languages
• High-Performance Computing
• +3 more

Bradford L. Chamberlain is a Distinguished Technologist at Hewlett Packard Enterprise and an Affiliate Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington. With over two decades of experience in high-performance computing, he has made significant contributions to parallel programming languages, particularly as the technical lead of the Chapel programming language project since 2006. His educational background includes: Ph.D. in Computer Science & Engineering from the University of Washington (2001) M.S. in Computer Science & Engineering from the University of Washington (1995) B.S. in Computer Science from Stanford University (1992) Chamberlain's research focuses on improving programmer productivity for high-performance computing through innovative language design, compiler techniques, and runtime systems. His work centers around the Chapel programming language, which aims to provide a multiresolution programming model that allows developers to express parallelism at varying levels of abstraction while maintaining performance across diverse architectures from laptops to supercomputers. His research spans parallel language design, compiler optimization, data distribution strategies, locality management, and performance portability. Chapel builds on his earlier work with the ZPL language, where he developed region-based approaches for sparse parallel computing. His publication record over the past fifteen years demonstrates a consistent focus on practical approaches to parallel programming, with recent work emphasizing data locality, heterogeneous architectures, and performance portability. His articles show an evolution from foundational language design concepts to increasingly sophisticated implementations addressing real-world HPC challenges, particularly in the areas of domain mapping, iterator abstractions, and memory management for large-scale systems. As a Distinguished Technologist at HPE, Chamberlain has played a key role in growing the Chapel project from a modest effort to one involving nearly 20 full-time developers. His leadership has positioned Chapel as one of the most promising languages for addressing the challenge of productive parallel programming at scale. He has secured funding, established collaborations with academia and industry, and performed extensive outreach through talks, tutorials, and research visits. At the University of Washington, Chamberlain serves as a liaison between academia and industry, participating in student committees, teaching graduate courses like Parallel Computation, and fostering communication between the department and HPE/Cray. His teaching experience spans from undergraduate data structures to graduate seminars on parallel programming environments. He has also volunteered as a tutor for underrepresented students in computer science.

David GreggView profile

Professor

• Software performance optimization
• Embedded systems
• Accelerating deep neural networks on embedded systems
• +12 more

David Gregg is a Professor in the Department of Computer Science at Trinity College Dublin's School of Computer Science and Statistics, where he serves as Global Director for Computer Science (since 2020) and previously as Head of the Discipline of Software and Systems (2018-2022). His research focuses on software performance optimization and embedded systems, with particular expertise in accelerating deep neural networks on resource-constrained platforms. He teaches Systems Programming (CS2014/5) and Concurrent Systems I (CS3014). Gregg's research spans multiple areas of computer systems including: Compiler optimization and program analysis Processor microarchitecture and parallelism (multi-core, vector, instruction-level) Computer arithmetic and domain-specific languages Low-energy embedded systems and FPGA implementations Deep neural network acceleration He has served on numerous program committees including PACT, PLDI, CC, and other major computer systems conferences, and has been on the Board of Distinguished Reviewers for ACM TACO multiple times. Professor Gregg has advised numerous PhD and MSc students, many of whom have gone on to prominent positions at companies like Intel-Movidius, Google, Amazon, and Synopsys. He leads the triNNity project which includes optimized libraries and compilers for implementing convolutional neural networks on CPUs.

Luc MarangetView profile

Researcher

• Weak Memory Models
• Concurrency
• Formal Verification
• +5 more

Luc Maranget is a Researcher at Inria Paris working within the Cambium project. His primary research focuses on weak memory models, concurrency, formal verification, and computer architecture. He has made significant contributions to understanding memory models in modern architectures including ARM, x86, and RISC-V. Maranget's research interests center around the formal modeling of memory consistency in modern processor architectures. He has developed theoretical frameworks for understanding relaxed memory models across multiple architectures and has created practical tools like the diy testing suite for validating memory models. His work bridges theoretical computer science with practical hardware implementation concerns, particularly in the domain of concurrent programming. His publication record shows a consistent focus on memory models and concurrency since 2016, with increasing emphasis on formal verification of hardware specifications. His research spans both theoretical aspects (operational semantics for memory models) and practical applications (testing suites, compiler implementations). Maranget teaches courses on programming shared memory multicore machines at MPRI (Master Parisien de Recherche en Informatique) and has previously taught at École polytechnique. He is also the author of H E V E A, a fast LaTeX to HTML translator, demonstrating his interest in programming language implementation. As the main developer of the diy testing suite, Maranget has created an important tool for the memory models research community. His work provides practical validation methods for theoretical models of processor behavior, making significant contributions to the verification of concurrent systems.

Santosh PandeView profile

Professor

• Program Analysis
• Software Security
• Compiler Optimizations
• +3 more

Santosh Pande is a Professor and Associate Chair for Graduate Studies in the School of Computer Science at Georgia Institute of Technology. His research focuses on compiler analysis and optimizations, providing deep insights into software behavior to improve various system properties through automated methods. His research interests include: Program Analysis for Security Compiler Optimizations and security implications Compiler-OS interactions for resource management Real-time software analysis Machine learning systems performance optimization Dr. Pande's recent publications demonstrate a strong focus on security-oriented compiler techniques, particularly in program debloating to reduce attack surfaces. His work addresses the critical intersection between compiler optimizations and security vulnerabilities, as well as innovative approaches to scheduling and resource allocation through compiler-OS collaboration. Research results show significant performance improvements (2x to 4x) for batch-oriented execution of modern workloads in data-center environments. His research has been consistently funded by: National Science Foundation (NSF) Office of Naval Research (ONR) Defense Advanced Research Projects Agency (DARPA) Air Force Industry partners including Sony, Toshiba, IBM, Motorola, and Infineon Dr. Pande holds a patent on smartcards developed in collaboration with Infineon. He actively mentors PhD students and seeks "smart and motivated PhD students" to join his research group. His work has resulted in over 100 publications and open-source software contributions. He is affiliated with multiple research centers at Georgia Tech including the Center for Experimental Research in Computer Systems (CERCS) and contributes to the Online Master of Science in Computer Science (OMSCS) program.

Joseph SchimmelsView profile

Professor

• Robotics
• Prosthetics
• Manufacturing
• +3 more

Joseph Schimmels is a Professor in the Mechanical Engineering department at Marquette University , where he also earned his B.S. in 1981. He serves as the Director of the Flexible Assembly Systems Network (FASN) , a collaborative platform between academia and industry focused on robotic manipulation, assembly, and material handling. His research spans intelligent design of multi-dimensional mechanical behavior , with applications in robotics , prosthetics , manufacturing , and vibration isolation . Ph.D., Mechanical Engineering, Northwestern University (1991) M.S., Mechanical Engineering, Northwestern University (1988) B.S., Mechanical Engineering, Marquette University (1981) Research interests center on implementing passive, programmable, and active compliance in robotic systems to enhance dexterity during contact tasks like assembly, sanding, and polishing. His work explores admittance matrix design , contact interaction analysis , and spatial compliance realization through mechanism design and variable stiffness actuators. Key publication trends include force-guided assembly under friction, spatial impedance control , and dual elastic mechanism synthesis using parallel/serial architectures. Scientific contributions are recognized through the Robert C. Greenheck Chair in Design and Manufacturing . He has mentored numerous students involved in FASN development projects, including Shuguang Huang , Jacob Frey , and Tony Carrasco , who have worked on robotic applications like 3-fingered VSA hands , Bananagrams-playing robots , and flashlight assembly systems . FASN emphasizes blending theory with hands-on application through workshops, software tools (MATLAB® compliance synthesis), and industry-partnered labs.

Michael LaverView profile

Professor

• History of East Asia
• Early Modern History
• History of Japan
• +5 more

Michael Laver is a Professor in the Department of History within the College of Liberal Arts at Rochester Institute of Technology (RIT). He concurrently serves as Associate Dean of the College of Liberal Arts, overseeing curriculum development, strategic planning, international education, and interdisciplinary programming. Previously, he chaired the Department of History and directed the International and Global Studies Program, while also holding university-wide roles including Chair of Academic Senate and co-chair of Middle States Re-accreditation. Outside academia, he serves as rector of Saint John's Episcopal Church in Sodus, New York. Education: B.A. in History and Psychology from Purdue University Ph.D. in East Asian Languages and Civilizations from the University of Pennsylvania Masters of Divinity from Colgate Rochester Crozer Divinity School Professor Laver's research spans History of East Asia , Early Modern History , History of Japan , History of Christianity , and History of Baseball . His scholarship examines Dutch-Japanese trade diplomacy through gift exchange, Tokugawa political strategies, and maritime networks in early modern East Asia. He analyzes how trade restrictions bolstered domestic hegemony while exploring cross-cultural encounters between European merchants and Japanese authorities. His 15 most recent publications reveal consistent focus on Dutch East India Company interactions with Tokugawa Japan, emphasizing gift-giving protocols, commodity exchanges, and diplomatic rituals. Recurring themes include cultural mediation through material objects, political uses of trade restrictions, and maritime borderlands. Parallel work addresses global religious history, particularly Christianity's Asian trajectories and baseball's historical development. Professor Laver collaborates on an NSF-funded initiative with Texas Tech University to integrate humanities into engineering education. Led by Iris Rivero, this project develops critical thinking and empathy skills in engineering students to address societal challenges, reflecting his commitment to interdisciplinary pedagogy.

Alastair F. DonaldsonView profile

Professor

• Programming Languages
• Compilers
• Verification
• +2 more

Alastair F. Donaldson is a Professor in the Department of Computing at Imperial College London, leading the Multicore Programming Group. His research focuses on programming languages, compilers, and automated testing of software systems. He previously directed GraphicsFuzz, an Imperial College spinout acquired by Google in 2018. Education: PhD in Computer Science (University of Glasgow), Postdoctoral Research Fellow (University of Oxford), Visiting Researcher (Microsoft Research Redmond) His research interests include: Compiler Design and Verification Randomized Testing Techniques Multicore and GPU Programming Formal Methods for Software Reliability Recent publications emphasize compiler fuzzing, metamorphic testing, and verification of GPU systems. He actively contributes to the development of testing tools for programming languages and hardware interfaces. Alastair holds leadership roles in academic conferences, including Publicity Co-Chair for POPL 2024 and committee roles in ASE, ECOOP, PLDI, and SPLASH. He maintains a personal website at http://www.doc.ic.ac.uk/~afd and has been registered on conf.researchr.org since 2015.

Marco VassenaView profile

Assistant Professor

• Programming Languages
• Security
• Compilers
• +7 more

Marco Vassena is an Assistant Professor at the Department of Information and Computing Sciences, Utrecht University. His research focuses on using programming language techniques like type systems, compilers, and program verification to build secure systems with reliable security guarantees. Affiliation: Utrecht University, Netherlands Research Areas: Language-based security, memory safety, constant-time programming, information flow control, WebAssembly security, and defenses against microarchitectural attacks. His work includes developing frameworks for secure execution environments, such as MSWasm for WebAssembly, and advancing tools like Blade to mitigate speculative leaks in cryptographic code. He has contributed to leading conferences including POPL, PriSC, and PLDI. Scientific Awards: Veni Grant (2023)

Andreas PavlogiannisView profile

Associate Professor

• Formal Methods
• Algorithmic Verification
• Automata Theory
• +6 more

Andreas Pavlogiannis is an Associate Professor in the Department of Computer Science at Aarhus University, Denmark, where he leads research in the Programming Languages group. His work focuses on formal methods, algorithmic verification, and concurrency analysis, with additional interests in network diffusion and evolutionary graph theory. He holds a PhD from IST Austria and actively recruits PhD students and PostDocs. Research Interests: Pavlogiannis investigates foundational and applied aspects of concurrent systems, including static/dynamic program analysis, automata theory, and weak memory models. His interdisciplinary work bridges computer science with evolutionary biology through network diffusion models and game theory. Awards: Distinguished Paper Award (PLDI 2025) Best Paper Award (ASPLOS 2024) Best Presentation Award (SOAP 2024) Best Paper Award (ASPLOS 2022) Teaching: He teaches courses on Programming Languages (Bachelor), Algorithmic Model Checking (Master), and Program Analysis (Master). Service: Serves on program committees for top conferences including POPL, PLDI, CAV, and IJCAI. Organizer of CONFEST 2025. Funding: Research supported by Villum Foundation, Danish Free Research Foundation (DFF), Stibo Foundation, and Austrian Science Fund (FWF).

Pascal RichardView profile

Professor

• Real-Time Systems
• Scheduling Algorithms
• Embedded Systems
• +5 more

Pascal Richard is a Full Professor specializing in Real-Time Systems at the Institute of Technology, University of Poitiers. He is affiliated with the LIAS (Laboratoire d'Ingénierie des Applications de la Résolution des Systèmes) laboratory, which has locations at both ENSIP (École Nationale Supérieure d'Ingénieurs de Poitiers) in Poitiers and ISAE-ENSMA (Institut Supérieur de l'Aéronautique et de l'Espace - École Nationale Supérieure de Mécanique et d'Aérotechnique) in Chasseneuil. His research spans over two decades with continuous publication from 1999 through 2023. Professor Richard's primary research interests focus on real-time scheduling theory, embedded systems, and avionics. His work particularly emphasizes AFDX networks , cache-related preemption delays , self-suspending tasks , and worst-case response time analysis . His research bridges theoretical foundations with practical applications in safety-critical systems, particularly in the aerospace domain. He has made significant contributions to the understanding of scheduling anomalies, feasibility analysis, and the development of approximation schemes for complex real-time problems. His publication record demonstrates strong collaboration with researchers across France and internationally, with consistent contributions to major real-time systems conferences including RTSS, ECRTS, and RTNS. His work shows an evolution from foundational scheduling theory toward increasingly complex systems including multiprocessor platforms, mixed criticality systems, and integrated modular avionics architectures. Professor Richard has contributed to the real-time community through numerous journal publications in Real-Time Systems , IEEE Transactions on Computers , and IEEE Transactions on Industrial Informatics , among others. His most recent work continues to address cutting-edge challenges in real-time scheduling for modern computing platforms.

Qingkai ShiView profile

Associate Professor

• Programming Languages
• Cybersecurity
• Software Engineering
• +3 more

Qingkai Shi is an Associate Professor in the School of Computer Science at Nanjing University, China, specializing in compiler techniques and formal program analysis for software and network security. His research bridges programming languages, cybersecurity, and software engineering with practical applications in real-world systems. Education: Ph.D. from Hong Kong University of Science and Technology Postdoctoral researcher at Purdue University, USA His research focuses on rigorous security validation through advanced static and dynamic analysis, particularly in network protocol parsers, compiler security, and autonomous systems. Key methodologies include context-sensitive program analysis, differential analysis, and formal specification techniques that address critical vulnerabilities in modern software ecosystems. Recent publications (2022-2026) demonstrate strong continuity in program analysis research with expanding applications to emerging domains like autonomous driving and Rust ecosystems. Work consistently targets high-impact security challenges in network protocols, compiler correctness, and memory safety, often yielding practical tools and industrial applications. Scientific Awards: Four ACM SIGPLAN/SIGSOFT Distinguished Paper Awards Google Research Paper Award Hong Kong Ph.D. Fellowship Dr. Shi co-founded Sourcebrella LLC (acquired by Ant Group), translating academic research into commercial security solutions. His ongoing industry collaborations demonstrate successful technology transfer from program analysis research. He leads an active research group developing open-source analysis tools including canary (alias analysis), netlifter (network protocol specification), and context-sensitive-reachability (data flow analysis), all available on GitHub with substantial community engagement.

Yan CaiView profile

Professor

• software testing
• program security
• concurrency bugs
• +4 more

Professor Yan Cai is a researcher and PhD supervisor at the Institute of Software, Chinese Academy of Sciences, with a focus on software testing, program security, and concurrency bugs. He holds a PhD from City University of Hong Kong and a BEng from Shandong University. His work spans multiple prestigious venues including ICSE, ASE, FSE, and IEEE Transactions on Software Engineering. Dr. Cai's educational background includes a PhD from City University of Hong Kong and a Bachelor of Engineering from Shandong University. His research interests primarily focus on software testing (particularly AI-based approaches), intelligent software systems analysis and testing, software security, and RISC-V software. He has made significant contributions to the field of concurrency bug detection and prediction. His recent publications demonstrate a strong trend toward applying AI techniques to software testing problems while maintaining rigorous theoretical foundations in concurrency analysis. His work bridges traditional program analysis with modern machine learning approaches, with applications ranging from autonomous driving systems to smart contract security. The research shows increasing focus on practical applications of theoretical concurrency models to real-world software systems. CCF NASAC-Neusoft Youth Software Innovation Award (2018) Excellent Advisor Award (2018) Young Elite Scientists Sponsorship Program (2017) Excellent Young AE Award (2016) Outstanding Reviewer (top 10%) for KDD 2025 Professor Cai has advised multiple PhD and Master's students including Biyun Zhu, Haicheng Li, Ruijie Meng, and Hao Yun. He serves as an Associate Editor for the Journal of Systems and Software and has been a program committee member for numerous top conferences including AAAI, ICSE, ASE, and FSE. His research has been supported through various grants, including the Young Elite Scientists Sponsorship Program from the China Association for Science and Technology and the China Computer Federation.

• Distributed Systems
• Erlang Programming Language
• Scalability Engineering
• +4 more

Natalia Chechina is an Honorary Research Fellow at the School of Computing Science, University of Glasgow, specializing in distributed systems with a particular focus on the Erlang programming language and its applications in building reliable and scalable systems. Her research interests span several critical areas in distributed computing: Distributed systems architecture and design Scalability and reliability engineering Erlang ecosystem development Robotics communication systems Server software engineering Performance optimization in distributed environments Dr. Chechina's extensive publication record from 2009-2021 demonstrates consistent contributions to advancing distributed computing capabilities, particularly through her work on SD Erlang (Scalable Distributed Erlang). Her research bridges theoretical analysis with practical implementation, addressing fundamental challenges in building systems that maintain functionality despite failures. She has made significant contributions to understanding how to construct robust server infrastructure that can scale effectively while preserving reliability across diverse application domains. Her collaborative work, frequently with Phil Trinder and other colleagues at the University of Glasgow, spans robotics, instant messaging systems, and general server infrastructure. The cross-disciplinary nature of her research is evident in publications addressing robot team coordination and communication, demonstrating how distributed systems principles can solve complex challenges in multiple domains.

Adwait JogView profile

Associate Professor

• Computer Architecture
• GPU Systems
• Memory Systems
• +6 more

Adwait Jog is an Associate Professor and Anita Jones Faculty Fellow in the Department of Computer Science at the University of Virginia. He holds a B.Tech. from National Institute of Technology, Rourkela, India (2009) and a Ph.D. from Pennsylvania State University (2015). His research focuses on GPU and accelerator-rich systems, emphasizing performance, energy efficiency, memory systems, and hardware security. His work is frequently published in top venues like IEEE/ACM conferences and funded by NSF and industry partners. Notable awards include the 2023 Plumeri Award for Faculty Excellence and a 2018 NSF CAREER Award. He teaches advanced courses on GPU architectures and computer systems design, and leads a research group addressing challenges in modern computing architectures. His lab explores topics like DNN acceleration, confidential computing, and GPU reliability through projects like TrioSim and Aspis.