Associate Professor at the Department of Computer Science , School of Computing , National University of Singapore . Research focuses on systems-level optimization across hardware-software stacks, including GPU computing, memory systems, and approximate computing for deep learning. Dr.Eng.Sc. (University of Tsukuba, 1993) M.Sc. (NUS, 1991) B.Sc. (NUS, 1989) Research interests span computer architecture , compiler design , and embedded systems , with recent emphasis on precision analysis , variable precision arithmetic , and deep learning approximation using hardware accelerators . Publications reveal trends in GPU optimization, memory management for NAND flash, and fault-tolerant cloud-based GPU computing. Scientific Recognition: Best Paper Finalist at IEEE High Performance Extreme Computing Conference (HPEC) 2017 Professional memberships include ACM Member and IEEE Senior Member , with editorial contributions to Software Practice and Experience . Teaching experience includes courses like CS2100 Computer Organisation and CS5250 Advanced Operating Systems .
Vasiliki Kalavri is an Assistant Professor in the Department of Computer Science at Boston University, where she co-leads the Complex Analytics and Scalable Processing (CASP) Systems lab. She holds a PhD from KTH Royal Institute of Technology and the Catholic University of Louvain (UCLouvain), awarded through the EMJD-DC joint doctoral program, and completed a postdoctoral fellowship at ETH Zurich, supported by the ETH Zurich Postdoctoral Fellowship. Her research focuses on distributed data processing, streaming computation, and large-scale graph analysis, with recent work emphasizing self-managed stream processing systems, secure collaborative analytics (via Multi-Party Computation), and scalable graph machine learning. Education includes a PhD (KTH/UCLouvain), MS (Polytechnic University of Catalonia), and undergraduate degrees from National Technical University of Athens (2010) and Polytechnic University of Catalonia (2012). She is a PMC member of Apache Flink and co-authored the textbook *Stream Processing with Apache Flink*. Her research contributions span foundational systems for stream processing (e.g., Strymon, CAPSys), secure analytics (SECRECY, TVA), and graph ML (GCNSplit, In situ Sampling). Awards include the ETH Zurich Postdoctoral Fellowship. She advises a team of PhD students focused on distributed systems and security. Teaching includes CS 551 (Streaming and Event-based Systems) and CS 210 (Computer Systems). Service roles include leadership in the BU-ACM Women student chapter and chairing the CS Graduate Awards Committee. Her work appears in top venues like OSDI, NSDI, EuroSys, and VLDB.
Fabian Scheler was a researcher at the Department of Computer Science 4 (Distributed Systems and Operating Systems) at Friedrich-Alexander University Erlangen-Nuremberg from 2005 to 2013. His research focused on reliable embedded real-time systems, culminating in his PhD thesis on Atomic Basic Blocks (ABB), which introduced a novel abstraction for manipulating real-time system architectures. He contributed to projects like the Real-Time Systems Compiler (RTSC), Aspect-Oriented Real-Time Architecture (AORTA), and Sloth, an interrupt-driven real-time operating system framework. Teaching activities included courses such as Real-Time Systems (since 2005), Dependable Real-Time Systems, and Concepts of Operating Systems components. Over 15 master’s and diploma theses were supervised, covering topics like real-time scheduling, compiler optimization, and embedded system reliability. Key research areas span real-time system design, compiler-driven architecture manipulation, and fault-tolerant embedded systems. Notable contributions include the RTSC framework for migrating event-triggered to time-triggered systems and Sloth’s hardware-based scheduling mechanisms. His work bridges theoretical compiler techniques with practical embedded system implementations. Contact details remain active at the university, including an office at Martensstr. 1, Erlangen, and email scheler@cs.fau.de. Publications span conferences like RTSS, IEEE SIES, and journals like Software: Practice and Experience, emphasizing real-time system reliability and compiler integration.
Tirthak Patel is an Assistant Professor in the Department of Computer Science at Rice University and Director of the Positive Technology Lab. His research focuses on systems-level challenges at the intersection of quantum computing and high-performance computing (HPC), emphasizing reliability, performance, and energy efficiency trade-offs. He holds a PhD from Northeastern University (2023) and prior degrees from Northeastern and the University of Toronto. Education: PhD in Computer Engineering, Northeastern University (2023) MS in Electrical and Computer Engineering, Northeastern University (2019) Bachelor of Applied Science in Electrical Engineering, University of Toronto (2017) His research explores quantum system software, compiler design for neutral atom quantum architectures, and quantum machine learning. Notable contributions include frameworks like PARALLAX (compiler for neutral atom quantum computers) and GEYSER (compilation for neutral atom systems). He prioritizes open-source tools and reproducible research. Research Trends in Publications: Recent work emphasizes quantum noise utilization, quantum GANs, and compiler optimizations for NISQ-era hardware. He also addresses challenges in hybrid quantum-classical systems and quantum cloud security (e.g., OpaQue for program obfuscation). Awards: 2024 ACM SIGHPC Doctoral Dissertation Honorable Mention 2021 ACM-IEEE CS George Michael HPC Fellowship 2024 Rice Outstanding Undergraduate Research Mentor Award Advising & Grants: While specific grant details aren't listed, his work is supported by open-source contributions and industry collaborations. He advises students through Rice's Quantum Computing programs and teaches courses like COMP 448/558: Quantum Computing Algorithms. Labs & Teams: Directs the Positive Technology Lab, focused on advancing quantum computing systems through interdisciplinary approaches. Collaborates with industry partners and international conferences as a TPC member for venues like SC, ISCA, and ICCAD.
Kanishkan Vadivel is a Researcher in the Electronic Systems group at Eindhoven University of Technology (TU/e), specializing in energy-efficient hardware architectures and compiler-based code-generation techniques. He holds a Master’s degree in Embedded Systems from TU/e (2017) and a Bachelor’s from Coimbatore Institute of Technology (India). Prior to academia, he worked in embedded systems at Tata Engineering and Arm Ltd. Research Interests : His work focuses on computation-in-memory architectures using resistive devices, optimal code generation for CGRA (Coarse-Grained Reconfigurable Architecture), and high-performance computing. Key projects include the MNEMOSENE initiative and development of the CIM-SIM simulator for computation-in-memory systems. Awards : HiPEAC collaboration grant (2019) Advising & Grants : His research is supported by grants focused on neuromorphic processors and edge-AI hardware. He collaborates on projects like NEUROKIT2E for embedded deep learning systems. Labs/Teams : Active member of TU/e’s Electronic Systems Center and Efficient Stream Processing Lab, contributing to neuromorphic and energy-efficient computing initiatives.
Muhammad Shahbaz is an Assistant Professor of Computer Science and Engineering at the University of Michigan , where he leads the NextGArch Lab . His research spans computer systems, networks, and architecture , focusing on domain-specific abstractions and programmable infrastructure for emerging workloads like machine learning and 5G networks. Postdoc, Electrical Engineering, Stanford University (2020) Ph.D. & M.A., Computer Science, Princeton University (2018) B.E., Computer Engineering, National University of Sciences and Technology (NUST) His work includes designing reconfigurable architectures for line-rate machine learning and next-generation networks . Recent publications explore in-network acceleration , DDoS detection , and SmartNIC optimization , reflecting his expertise in networking systems and domain-specific compilers . Notable honors include the NSF CAREER Award (2024) , Google Research Scholar Award (2024) , and SRC JUMP 2.0 Best Paper Award (2024) . He mentors students in systems research and collaborates on projects like the NSF Convergence Accelerator Phase 1 Award for Track G.
Antonio Paolillo is a Professor in the Department of Informatics and Applied Informatics at Vrije Universiteit Brussel. His research focuses on real-time systems, embedded software, robotics, and synchronization protocols. He leads projects like Brubotics (sustainable human-centered robotics) and FORCES (reliable robotic systems), emphasizing safety, privacy, and performance in human-robot collaboration. Key contributions include the mmPrivPose3D dataset for gesture recognition and sensor-based safety systems. He actively contributes to conferences like ECRTS 2025 and is involved in OS design for embedded platforms. His work bridges theoretical formal verification with practical implementations in multi-core and NUMA architectures. Education details and specific degrees were not explicitly mentioned in the provided text. Research interests span real-time scheduling, hardware-software co-design, and robust embedded systems. Recent articles emphasize privacy-compliant human-robot interaction and compiler transpilation for safety-critical applications. He collaborates internationally in robotics and real-time systems domains. Current projects (2024-2029) include foundational work on embedded software performance, reconfigurable robotics, and conference organization for ECRTS 2025. His work often involves interdisciplinary teams and industry partnerships.
Martha Kim is an Associate Professor of Computer Science at Columbia University's Fu Foundation School of Engineering and Applied Science. She serves as a member of the Data Science Institute, co-chairs the Center for Computing Systems for Data-Driven Science, and chairs the Computer Engineering Program. Her academic appointments span multiple research centers and educational initiatives at Columbia. Dr. Kim earned her PhD in Computer Science and Engineering from the University of Washington and completed her undergraduate studies in Computer Science at Harvard University. Her educational background has provided a strong foundation for her research and teaching career in computer systems. Her research interests focus on the intersection of hardware and software systems, specializing in computer architecture, parallel programming, compilers, and low-power computing. Dr. Kim's work explores innovative approaches to hardware accelerator design, with particular emphasis on improving usability of accelerators and developing data-centric accelerator architectures. Her research has investigated low-cost chip manufacturing systems, reconfigurable communication networks, and fine-grained parallel application profiling techniques. The publication record reveals a consistent research trajectory focused on hardware-software co-design, with recent work emphasizing practical implementations of architectural concepts. Her articles demonstrate expertise across multiple subfields including thermal management, database acceleration, and energy-efficient computing, with publications appearing in top-tier conferences like ASPLOS, MICRO, and ISLPED. Rodriguez Family Award (2013) Edward and Carole Kim Faculty Involvement Award (2015) NSF CAREER award (2013) Anita Borg Early Career Award (2016) Dr. Kim actively mentors doctoral students through the ARCADE Lab, with current advisees including Martha Barker, Thomas Repetti, and Andrea Lottarini, and previously guiding Melanie Kambadur (PhD 2016) and Lisa Wu (PhD 2014). Her research has received substantial funding from major organizations including C-FAR, DARPA, Google, Intel, and the National Science Foundation, enabling significant contributions to computer architecture research. She leads the ARCADE Lab at Columbia University, which serves as the primary research hub for her team's work on computer architecture and systems. The lab environment fosters collaboration between faculty, graduate students, and industry partners to advance research in hardware acceleration and energy-efficient computing.
Dr. Deepayan Bhowmik is a Senior Lecturer and Director of Research at Newcastle University's School of Computing. He holds a PhD in Electronic and Electrical Engineering from the University of Sheffield. His research focuses on image/signal processing, AI, neuromorphic vision systems, and their applications in media security, remote sensing, and space research. He actively contributes to UN Sustainable Development Goals related to clean water, environmental sustainability, and responsible consumption. Grants & Collaborations: PI of £2M EPSRC-funded North East Space Communications Accelerator (2025-2029) Co-I in Airbus-funded Smart Earth Observation Satellite Constellation project (2024-2028) Lead on JPEG Trust international standard for media authenticity Research Interests: Combines theoretical advancements in signal processing with practical applications in media forensics, environmental monitoring, and heterogeneous computing. Recent work addresses AI-generated media manipulation detection and satellite imagery analysis for ecological challenges like water hyacinth infestation. Publications: Over 28 peer-reviewed articles spanning watermarking techniques, FPGA optimization, and remote sensing applications. Recent trends show increasing focus on AI-driven media security and space-based earth observation systems.
Emilio ARNIERI is an Associate Professor at the Department of Computer, Modeling, Electronics and System Engineering (DEIS) of the University of Calabria , Italy. His research focuses on microwave engineering , antenna design , and satellite communication systems , with particular emphasis on phased arrays , dielectric spectroscopy , and 5G/6G technologies . Academic Rank: Associate Professor Key Research Areas: Antenna Design, Microwave Sensors, Millimeter-Wave Communication Current Affiliation: University of Calabria (DEIS department) His recent work explores K/Ka-Band systems for SatCom-on-the-Move , hybrid multi-band sensors for microfluidic applications, and low-profile antennas for automotive and satellite use. Publications from 2023-2025 reveal a focus on dielectric spectroscopy , beamforming , and SIW (Substrate Integrated Waveguide) technology. Notable projects include the QV-Lift Project for satellite ground segments and BiCMOS integration for high-frequency applications. Recent articles indicate expertise in transmitarray antennas , vector modulators , and reconfigurable intelligent surfaces for 5G backhaul systems. Collaborations span satellite communication , automotive radar , and millimeter-wave infrastructure .
Dr.-Ing. Gerald Hempel is a researcher at Dresden University of Technology (TU Dresden) with active contributions to computer architecture and embedded systems from 2015–2023. His work bridges hardware/software co-design through domain-specific languages and compiler techniques, primarily within the Faculty of Electrical and Computer Engineering context. His research spans: Domain-Specific Languages for hardware acceleration Memory optimization in high-performance computing Reconfigurable computing using FPGAs Many-core and heterogeneous system design Bio-inspired algorithms for robust system mapping Racetrack memory applications in brain-inspired cognition Publication analysis reveals consistent focus on compiler-driven hardware acceleration, particularly for computational fluid dynamics and cognitive systems. His work emphasizes memory architecture innovations (e.g., high-bandwidth memory, caching) and bio-inspired robustness techniques, often through collaborations like the EVEREST consortium for compilation frameworks. No scientific awards were documented in the source material. No student advising or grant information was provided in the available texts. Dr. Hempel collaborates within TU Dresden's research ecosystem, notably with the EVEREST consortium and chairs including Compiler Construction and Emerging Electronic Technologies. His work on tools like Mocasin demonstrates active participation in teams developing rapid prototyping frameworks for heterogeneous multi-core systems and FPGA-based accelerators.
Dr. Michael Jipping is a Professor of Computer Science and Department Chair at Hope College, where he has served since 1987. His expertise spans assistive technology, mobile software development, and computer security, with a focus on leveraging smartphones for accessibility. Education : Ph.D. (1986), M.S. (1984) in Computer Science from the University of Iowa; B.S. (1981) in Computer Science from Calvin College. His research emphasizes assistive technologies for low-vision users and cognitive disabilities, alongside mobile operating systems and network security. Recent publications include work on augmented reality applications and mobile education frameworks. Grants include funding for undergraduate research in biomedical applications (2009) and classroom technology innovations (1996–2003). Outside academia, he is active in community and church life, with interests in camping, photography, and science fiction.
Dr. Zhiru Zhang is a Professor in the School of Electrical and Computer Engineering at Cornell University and a member of the Computer Systems Laboratory. His research focuses on new algorithms, methodologies, and design automation tools for heterogeneous computing systems, with recent publications centering on high-level synthesis (HLS), hardware specialization for machine learning, and programming models for software-defined FPGAs. Dr. Zhang earned his Ph.D. in Computer Science from UCLA, where he co-founded AutoESL based on his dissertation research on HLS. AutoESL was acquired by Xilinx (now AMD), and its HLS tool evolved into Vivado HLS (now Vitis HLS), which is widely used for designing FPGA-based hardware accelerators. He also holds a B.S. in Computer Science from Peking University and an M.S. in Computer Science from UCLA. Dr. Zhang's research interests span hardware design, high-level synthesis, FPGA acceleration, machine learning acceleration, heterogeneous computing systems, and computer architecture. His work bridges the gap between software algorithms and hardware implementation, focusing on creating efficient design automation tools that enable specialized hardware for emerging applications, particularly in AI and machine learning. His recent publications demonstrate strong trends in differentiable programming for hardware design, sparse computation optimization, and efficient implementation of large language models on FPGAs. Dr. Zhang has received numerous prestigious awards including being named an IEEE Fellow, the Intel Outstanding Researcher Award, AWS AI Amazon Research Award, Facebook Research Award, Google Faculty Research Award, DAC Under-40 Innovators Award, Rising Professional Achievement Award from UCLA, DARPA Young Faculty Award, IEEE CEDA Ernest S. Kuh Early Career Award, and NSF CAREER Award. His papers have won multiple Best Paper Awards from top conferences including ASPLOS (2025), ISPD (2025), FPGA (2024, 2022, 2021, 2019), AutoML (2024), FCCM (2018), ACM TODAES (2012), and Top Picks in Hardware and Embedded Security (2020). His papers on HLS scheduling and application-specific instruction-set processor (ASIP) compilation have been inducted into the ACM/SIGDA TCFPGA Hall of Fame for the classes of 2022 and 2023, respectively. On the teaching side, Dr. Zhang has received the Ruth and Joel Spira Award for Excellence in Teaching (2018) and twice the Michael Tien'72 Excellence in Teaching Award (2016, 2022), the highest recognition for teaching in the College of Engineering. He teaches courses including ECE 5775/6775: High-Level Digital Design Automation, ENGRD/ECE 2300: Digital Logic and Computer Organization, ECE 6980: Special Topics on Hardware Acceleration of Deep Learning, ENGRG 1050: Freshman Engineering Seminar, and ECE 5950: Special Topics on High-Level Digital Design Automation. Dr. Zhang leads an active research group with numerous PhD students and postdocs. His current students include Jordan Dotzel, Jie Liu, Zichao Yue, Yixiao Du, Yaohui Cai, Andrew Butt, Hongzheng Chen, Jiajie Li, Niansong Zhang, Matthew Hofmann, Zhanqiu Hu, Vesal Bakhtazad, and Grace Dinh. His alumni have gone on to successful careers at companies like NVIDIA, Google, AWS AI, Meta, Microsoft, and academic positions at universities including University of Illinois Chicago and Zhejiang University. The group has received multiple research grants from industry partners including AWS, Intel, and Google.
Professor Murray Cole is a faculty member at the School of Informatics , University of Edinburgh, holding the Personal Chair of Patterned Parallel Computing. He is affiliated with the Institute for Computing Systems Architecture and co-directs the Centre for Doctoral Training in Pervasive Parallelism . As a PGR Personal Tutor, he provides academic support for research students. His research focuses on parallel programming models , particularly skeletons—abstractions for structuring parallel programs. Key areas include performance portability across architectures (GPUs, manycore, clusters), dynamic optimization, and domain-specific languages. Projects like Transmuter and CoSPARSE highlight his work in reconfigurable hardware and graph analytics. He contributes to postgraduate teaching through the course Parallel Programming Languages and Systems . While no explicit scientific awards are listed, his leadership in major EPSRC-funded projects underscores his impact in compiler design and computer architecture.
Qian Xu is a Sherman Fairchild Postdoctoral Scholar Research Associate at the Walter Burke Institute for Theoretical Physics, California Institute of Technology (Caltech), supervised by John Preskill. Their research focuses on quantum error correction and fault-tolerant quantum computing within Caltech's theoretical physics ecosystem. Education: Ph.D. in Quantum Science and Engineering, University of Chicago (2024), advised by Liang Jiang. Thesis: 'Towards Practical Fault-Tolerant Quantum Computing'. B.S. in Physics, Nanjing University (2019). Research Interests: Xu pioneers approaches to minimize space-time overhead in fault-tolerant quantum systems through novel error-correcting codes and noise-robust processor design. Their work integrates quantum error correction, quantum control, and reservoir engineering to develop practical quantum computing architectures. Key innovations include tailored codes for biased noise environments and hardware-efficient protocols for bosonic qubit systems. Current investigations span quantum LDPC codes, homological product codes, and cat qubit stabilization techniques. Publication Trends: Xu's 12 publications (2021-2024) reveal three dominant research thrusts: (1) Low-overhead fault tolerance using quantum LDPC and homological product codes; (2) Hardware-efficient bosonic qubit systems (cat/squeezed cat codes); (3) Noise-adaptive topological code design. This work demonstrates consistent focus on reducing physical resource requirements while maintaining fault tolerance, with increasing emphasis on experimental feasibility through collaborations with quantum hardware groups. Labs and Teams: As a member of Caltech's Walter Burke Institute for Theoretical Physics, Xu collaborates extensively with the Preskill research group and experimental teams at Harvard/MIT. Their work bridges theoretical quantum information science and near-term quantum device engineering through the Institute's cross-disciplinary framework.
