Dr. Roel Jordans is an Assistant Professor specializing in hardware architectures and compilation techniques at Eindhoven University of Technology. His research develops efficient systems for reliable high-performance computing and application-specific processors. Research Focus: Hardware accelerators, reconfigurable computing platforms, and compilation methods for specialized processors. Current projects include neuromorphic edge computing and radio astronomy instrumentation. Awards: Recognized for research excellence with Best Paper awards at leading conferences in digital system design and embedded computing.
Jürgen Teich is a Professor at the University of Erlangen-Nuremberg, Department of Computer Science. His research focuses on computer architecture, embedded systems, and hardware-software co-design, with particular emphasis on energy-efficient and sustainable computing. He leads projects involving FPGA-based accelerators, neural networks on microcontrollers, and real-time systems optimization. His work spans topics such as approximation computing, MPSoCs (Multiprocessor Systems-on-Chip), and IoT device architectures. Key contributions include methodologies for optimizing resource allocation in heterogeneous systems and developing energy-harvesting solutions for embedded systems. Teich has authored numerous publications in top-tier conferences and journals, including DATE, FPL, and ACM Transactions. His research often collaborates with industry partners, emphasizing practical applications and open-source hardware.
Kevin Angstadt is an Assistant Professor of Computer Science at St. Lawrence University, part of the Department of Mathematics, Computer Science, and Statistics. He holds a Ph.D. from the University of Michigan (2020) and an MCS from the University of Virginia (2016), with undergraduate degrees in Computer Science, Mathematics, and German Studies from St. Lawrence University (2014). His research focuses on the intersection of computer architecture, programming languages, and software engineering, with an emphasis on optimizing programming support for emerging hardware technologies like accelerators and autonomous systems. Education: Ph.D. in Computer Science and Engineering, University of Michigan (2020) M.S. in Computer Science, University of Virginia (2016) B.S. in Computer Science, Mathematics, and German Studies, St. Lawrence University (2014) Research Interests: His work spans programming abstractions for hardware accelerators, fault-tolerant autonomous systems, and tools like MNRL and MNCaRT for automata processing. He also collaborates on projects such as StatKey, a statistical simulation tool used by over one million users. Recent Articles Trends: His publications emphasize hardware-software co-design, resilience in autonomous systems, and debugging support for pattern-matching languages. Recent work includes NSF-funded research on program repair and optimization, and frameworks like LOGI and START for secure autonomous vehicle operation. Awards: NSF Medium Grant ($1.2M, 2022) UVA Teaching and Service Award (2017) Jefferson Scholars Foundation Fellow (2014–2017) Best in Session Award at TECHCON 2016 Advising & Grants: He leads a $1.2M NSF grant and has advised projects on pattern-matching accelerators, autonomous vehicle resilience, and compiler optimization. Collaborates with industry and academic partners on mission-critical systems and software reliability. Labs/Teams: Core contributor to MNRL (automata processing ecosystem), StatKey (statistical tools), and the START project for resilient autonomous systems. Active in open-source development and hardware-accelerator research groups.
Nachiket Kapre is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, Canada (2023–present). He previously held positions as Associate Professor (2016–2021) and on leave as Research Director at Xilinx Labs (AMD Research, Singapore, 2022–2023). Before that, he was an Assistant Professor at Nanyang Technological University (NTU), Singapore (2012–2016) and a Junior Research Fellow at Imperial College London (2010–2012). He earned a Ph.D. and two M.S. degrees from the California Institute of Technology (2010), and a B.E. from the University of Pune (2002). His research focuses on Concurrent and Spatial Architectures , Parallel Processing , and Communication-Centric Design , with a strong emphasis on FPGA-based acceleration for applications like machine learning, graph algorithms, and embedded systems. Key contributions include Hoplite NoC architectures and CaffePresso for deep learning acceleration. Notable awards include the FPT Best Paper Award (2024), TRETS Best Paper Award (2023), and the CASES 2016 Best Paper Award. He has led multiple grants, including NSERC Discovery Grants and A*STAR-funded projects. His advising spans 15+ students across PhD and MSc levels, contributing to FPGA toolflows, NoC design, and hardware acceleration. He has authored over 50 publications in top venues like FPGA, FPL, and ACM TRETS, and serves as a program chair for FCCM 2023. His work bridges theory and practice, emphasizing energy-efficient computing and reconfigurable systems.
Dr. Dong Kai Wang is a Teaching Assistant Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research focuses on leveraging machine learning for computer architecture advancements, particularly in CPU and accelerator microarchitecture design. He is interested in improving system performance and energy efficiency through innovative hardware solutions. Wang's recent work, supported by a grant from Samsung, explores using accelerators to offload tasks traditionally handled by CPUs, aiming to enhance efficiency without major architectural overhauls. His approach involves a lightweight controller to translate CPU machine code for use on reconfigurable accelerators, minimizing chip area costs while maximizing performance gains. This research builds on his doctoral work under Nam Sung Kim, now a co-PI on the project. He has contributed to the field through editorships in journals such as Integration, the VLSI Journal and IEEE Transactions on Computers. His efforts have been recognized with the AMD HACC Outstanding Researcher Award (2024). Wang teaches courses in digital systems, computer organization, and VLSI system design, reflecting his commitment to both research and education. Wang has also secured a patent (US-20240211393-A1) for "Leveraging Processing in Memory Registers as Victim Buffers," further underscoring his innovative contributions to hardware design. His research lab focuses on advancing hardware-software co-design and next-generation computing architectures.
Eduard Ayguade Parra is a Full Professor in the Department of Computer Architecture at the Universitat Politècnica de Catalunya (UPC), Faculty of Computer Science of Barcelona (FIB). He is a leading researcher in the UPC PM - Programming Models group and maintains a significant affiliation with the Barcelona Supercomputing Center (BSC-CNS), a premier national supercomputing facility. His primary research interests lie in High-Performance Computing (HPC) , with a deep focus on parallel and distributed architectures , programming models (especially task-based models like OmpSs), multicore and multiprocessor systems , and compilers for high-performance architectures . His work bridges hardware and software to optimize performance for complex computational problems. The trends in his recent publications highlight a sustained and evolving research program. He is actively advancing task-based programming for distributed memory and hybrid systems, exploring FPGA acceleration for key HPC kernels like SpMV, and innovating in memory system design, including active compute memory and hybrid memory object placement. His research also extends into applying AI techniques to hardware reliability and creating high-quality datasets for computer vision evaluation. HiPEAC Paper Award 2024 Professor Ayguade has been instrumental in securing and leading numerous competitive and non-competitive R&D+i projects, often funded by national and European programs. He has advised a significant number of doctoral students, whose theses cover topics such as task-based programming, FPGA acceleration, HPC compilers, and machine learning for systems. His collaborations are extensive, with frequent co-authorship with prominent figures at UPC and BSC-CNS, such as Jesús Labarta and Mateo Valero. His research has led to advancements in runtime systems, compiler technology, and FPGA-based acceleration. He is a core member of the UPC PM - Programming Models research group and his work is deeply integrated with the resources and mission of the Barcelona Supercomputing Center (BSC-CNS), one of Europe's leading institutions in supercomputing.
Christopher Terman is a Senior Lecturer (Emeritus) at the Massachusetts Institute of Technology (MIT), affiliated with the School of Engineering and the Department of Electrical Engineering and Computer Science (EECS). He holds office in 32-G790 and can be reached at cjt@mit.edu. His research interests span digital communication systems, VLSI design methodologies, and educational technology innovations in engineering education. Terman has contributed extensively to the development of simulation tools for digital integrated circuits and has pioneered interactive learning environments for VLSI design education. His work integrates theoretical advancements with practical applications in both industry and academia. Over his career, Terman has authored influential papers on topics ranging from multiprocessor architectures to compiler optimization techniques, reflecting his interdisciplinary expertise in electrical engineering and computer science. His educational contributions include the design of MIT's 6.004 Computation Structures course, emphasizing scalable and learner-centered pedagogical strategies. Terman's publications demonstrate a sustained focus on bridging computational theory with real-world implementation challenges, particularly in the realms of digital signal processing and embedded systems. While no formal scientific awards are listed, his long-term academic leadership and contributions to foundational engineering education have had lasting impacts on both the field and MIT's curriculum. His work continues to inform modern approaches to integrating simulation, design automation, and collaborative learning in technical disciplines.
Rob A. Rutenbar is the Senior Vice Chancellor for Research at the University of Pittsburgh and holds Distinguished Professor appointments in the School of Computing and Information and Swanson School of Engineering. He previously served as Head of Computer Science at the University of Illinois (2010-2017) and chaired Electrical and Computer Engineering at Carnegie Mellon University for 25 years. His research focuses on integrated circuit design tools, nanoscale statistical modeling, and hardware accelerators for AI. He founded companies Neolinear (acquired by Cadence) and Voci Technologies (acquired by Medallia). Rutenbar has authored over 200 publications and mentored 50+ students. He is an ACM/IEEE Fellow and recipient of the Phil Kaufman Award and ACM SIGDA Pioneering Achievement Award. Education: PhD in Computer Engineering (University of Michigan, 1984), MS (1979), BS in Electrical Engineering (Wayne State University, 1978). Research Interests: Tools for analog IC design, statistical models for nanoscale circuits, and AI hardware architectures. Notable projects include the Center for Circuit & System Solutions (C2S2) and the first EDA MOOC on Coursera with 100k+ learners. Awards: Includes ACM SIGDA Pioneering Achievement Award (2021), AAAS Fellow (2019), Phil Kaufman Award (2017), and Donald O. Pederson Best Paper Award (2011, 2013). Leadership: Launched Pitt Momentum Funds, LifeX Labs, and the CS+X interdisciplinary degree program at Illinois. Serves as Chair-Elect of the APLU Council on Research.
Mark Horowitz holds the Fortinet Founders Chair in Electrical Engineering and is the Yahoo! Founders Professor in Stanford University's School of Engineering. He also serves as Professor of Computer Science. His career spans over four decades, with foundational contributions to microprocessor design, high-speed link architectures, and computational photography innovations like the Lytro camera. Education: PhD in Electrical Engineering, Stanford University (1984) MS in Electrical Engineering, MIT (1978) BS in Electrical Engineering, MIT (1978) Research Interests: His work bridges EE and CS with interdisciplinary focus on: Agile hardware design methodologies for VLSI systems High-speed signaling and memory interfaces (e.g., Rambus technology) Reconfigurable computing architectures (e.g., CGRA-based accelerators) Applications in computational biology and molecular systems Recent Directions: Recent publications emphasize energy-efficient accelerators for machine learning, memory subsystem innovations, and compiler-driven hardware design frameworks like AHA! His work on Onyx and Opal architectures demonstrates leadership in sparse tensor computation hardware. Labs & Teams: Leads the Stanford VLSI Research Group and AHA! initiative. Collaborations include work with Prof. Marc Levoy on computational imaging and partnerships with industry on memory interface standards.
David Speck is a postdoctoral researcher at the University of Basel , Switzerland, affiliated with the Department of Mathematics and Computer Science . He previously held positions at the Machine Reasoning Lab (Linköping University, Sweden) and the Chair of Foundations of Artificial Intelligence (University of Freiburg, Germany), where he earned his PhD in 2022. Bachelor's (2015) and Master's (2018) in Computer Science from the University of Freiburg. PhD (Dr. rer. nat.) in 2022 from the University of Freiburg. His research focuses on Artificial Intelligence , particularly automated planning , symbolic search , and heuristic optimization . He explores techniques like cost partitioning , plan space navigation , and expressive planning formalisms (e.g., axioms, conditional effects, state-dependent costs). Recent work includes modeling matrix multiplication algorithms and analyzing symmetry breaking in planning. From 2021–2025, his publications span conferences like KR , ECAI , AAAI , and journals such as Journal of Artificial Intelligence Research . Key contributions include methods for perfect saturated cost partitioning , symbolic search with performance guarantees , and plan space counting and reasoning . His work often bridges theoretical analysis with practical planner implementations (e.g., AxSAT , SymK ). He collaborates with researchers like Jendrik Seipp , Daniel Gnad , and Malte Helmert , and has contributed to competitive planner development (e.g., Ragnarok , Odin ).
Weija Shang is a Professor at the School of Engineering, Santa Clara University, where she has been since 1994. She previously served at the Center for Advanced Computer Studies, University of SW Louisiana (1990–1993). Her research spans parallel processing, computer architecture, parallelizing compilers, algorithm theory, and non-linear optimization. PhD in Computer Engineering, Purdue University (1990) MS in Computer Engineering, Purdue University (1984) BS in Computer Engineering, Changsha Institute of Technology (1982) Her publications focus on parallel computing , GPGPU optimization , FPGA design , and video coding techniques. Key themes include supernode transformations , media distribution algorithms , and stack optimization in recursive programs. Scientific awards include: Clare Boothe Luce Professor (1994–2000) NSF Research Initiation Award (1991) NSF Career Award (1995) She has supervised numerous research projects in parallel programming and compiler design, contributing to high-performance computing and distributed systems through collaborations with institutions like Xilinx and NASA.
Richard Membarth is an academic researcher at the Friedrich-Alexander-Universität Erlangen-Nürnberg, Department of Computer Science. His work focuses on high-performance computing, domain-specific compilers, and GPU acceleration. He has contributed to projects like FLOWER (dataflow compiler), Hipacc (image processing DSL), and XEngine (neural network optimization). Membarth's research bridges compiler design, parallel algorithms, and heterogeneous hardware, with applications in medical imaging, bioinformatics, and autonomous systems. Co-developer of AnyDSL framework for partial evaluation Lead in GPU acceleration for molecular dynamics (tinyMD) Specialized in compiler techniques for FPGAs and GPUs Key areas include: - Domain-specific languages (DSLs) - Parallel algorithm optimization - Medical computing pipelines - Real-time graphics rendering
Suprio Ray is an Associate Professor in the Faculty of Computer Science at the University of New Brunswick, Canada, leading the Big Data Systems and Analytics Lab. He holds a PhD from the University of Toronto, an M.Sc. from the University of British Columbia, and a B.E. from NIT Trichy. Previously, he worked in industry roles at Oracle, Bell Labs, and Webtech Wireless, and completed a PhD internship at SAP. His research focuses on scalable data systems, spatial/spatio-temporal data management, and modern hardware utilization. Key projects include the Jackpine spatial database benchmark , DaskDB (a scalable data science system), and NUMA-aware query processing . He collaborates across disciplines with ECE and GGE departments, supported by grants from NBIF, NSERC, and industry partners. Research interests span Big Data systems, privacy/security in databases, blockchain analytics, and parallel/distributed computing. He has pioneered techniques like STILT multi-dimensional indexes , privacy-preserving spatial queries (Pystin) , and learned spatial indexes . Over 60 publications appear in top venues like SIGMOD, ICDE, and IEEE BigData. Education: PhD (Computer Science), University of Toronto (2015) M.Sc. (Computer Science), University of British Columbia (2003) B.E. (Computer Science & Engineering), NIT Trichy (2000) Teaching includes courses on big data systems (CS4545/6545), database foundations (CS6585), and data science (CS2545). He advises graduate students in scalable analytics and spatial systems, emphasizing industry-relevant software skills. Key awards include the 2024 ACM SIGSPATIAL best poster award , IBM Best Student Paper (2014) , and Harrison McCain Foundation award (2016) . His work has been recognized with 7 best paper awards and 3 patents. Current projects explore FPGA-accelerated joins , serverless data analytics , and privacy-preserving blockchain queries . Past contributions include the GEMM mobility model (2003) and foundational spatial benchmarks.
Associate Professor at the Department of Computer Science , School of Computing , National University of Singapore . Research focuses on systems-level optimization across hardware-software stacks, including GPU computing, memory systems, and approximate computing for deep learning. Dr.Eng.Sc. (University of Tsukuba, 1993) M.Sc. (NUS, 1991) B.Sc. (NUS, 1989) Research interests span computer architecture , compiler design , and embedded systems , with recent emphasis on precision analysis , variable precision arithmetic , and deep learning approximation using hardware accelerators . Publications reveal trends in GPU optimization, memory management for NAND flash, and fault-tolerant cloud-based GPU computing. Scientific Recognition: Best Paper Finalist at IEEE High Performance Extreme Computing Conference (HPEC) 2017 Professional memberships include ACM Member and IEEE Senior Member , with editorial contributions to Software Practice and Experience . Teaching experience includes courses like CS2100 Computer Organisation and CS5250 Advanced Operating Systems .
Vasiliki Kalavri is an Assistant Professor in the Department of Computer Science at Boston University, where she co-leads the Complex Analytics and Scalable Processing (CASP) Systems lab. She holds a PhD from KTH Royal Institute of Technology and the Catholic University of Louvain (UCLouvain), awarded through the EMJD-DC joint doctoral program, and completed a postdoctoral fellowship at ETH Zurich, supported by the ETH Zurich Postdoctoral Fellowship. Her research focuses on distributed data processing, streaming computation, and large-scale graph analysis, with recent work emphasizing self-managed stream processing systems, secure collaborative analytics (via Multi-Party Computation), and scalable graph machine learning. Education includes a PhD (KTH/UCLouvain), MS (Polytechnic University of Catalonia), and undergraduate degrees from National Technical University of Athens (2010) and Polytechnic University of Catalonia (2012). She is a PMC member of Apache Flink and co-authored the textbook *Stream Processing with Apache Flink*. Her research contributions span foundational systems for stream processing (e.g., Strymon, CAPSys), secure analytics (SECRECY, TVA), and graph ML (GCNSplit, In situ Sampling). Awards include the ETH Zurich Postdoctoral Fellowship. She advises a team of PhD students focused on distributed systems and security. Teaching includes CS 551 (Streaming and Event-based Systems) and CS 210 (Computer Systems). Service roles include leadership in the BU-ACM Women student chapter and chairing the CS Graduate Awards Committee. Her work appears in top venues like OSDI, NSDI, EuroSys, and VLDB.
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