Hyesoon Kim is a Professor at the Georgia Institute of Technology , affiliated with the College of Computing and leading the HPArch research group . She co-directs the Center for Research into Novel Computing Hierarchies (CRNCH) . Her research focuses on Computer Architecture , GPU , Compilers and Runtime Systems , and Hardware Security , particularly for heterogeneous systems. Contact : hyesoon@cc.gatech.edu Location : 266 Ferst Drive, KACB 2344, Atlanta, GA Research Trends Her recent work spans RISC-V extensions for security, CUDA optimization on softcore GPUs, memory safety techniques, and energy-efficient deep learning architectures. Articles emphasize heterogeneous computing , GPU performance scaling, and IoT -oriented neural network methods. Open Source Projects She leads development of Macsim (heterogeneous architecture simulator) and Vortex (open-source GPU platform).
Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. She leads the Stanford Accelerate research group, focusing on domain-specific hardware architectures and agile hardware-software co-design. Her work emphasizes high-performance, energy-efficient accelerators for emerging technologies. Education: B.Tech. from IIT Delhi (2011), M.S. and Ph.D. from MIT (2013/2018). Postdoctoral experience includes NVIDIA Research (2018) and Amazon Visiting Academic (2023–present). Awards include the Sloan Research Fellowship (2024), NSF CAREER Award (2023), and Terman Faculty Fellowship (2018). Research Interests: Domain-specific architectures, near-memory computing, design productivity, and machine learning acceleration. Her group develops frameworks like AHA (Agile Hardware) for efficient accelerator design and compilers. Awards: Over 10 major awards, including best paper recognitions at VLSI, MICRO, and JSSC. Active roles as Associate Editor for IEEE JSSC and Program Chair for IEEE Hot Chips (2020). Advising & Teaching: Supervises multiple PhD and MS students in hardware design, CGRAs, and ML accelerators. Teaches VLSI design courses (EE271/272/372) and oversees independent studies in embedded systems and chip design. Labs & Collaborations: Affiliated with Stanford PORTAL Center, AHA Center, and SystemX Alliance. Projects include MINOTAUR (edge AI accelerator), Amber (CGRA-based SoC), and EMBER (RRAM macros).
Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.
Michael Baldea is an Associate Professor in the Department of Chemical Engineering at the University of Texas at Austin . He holds a Ph.D. in Chemical Engineering from the University of Minnesota (2006), with prior degrees from 'Babeş-Bolyai' University in Romania (M.Sc. 2001, Diploma 2000). His research group develops theoretical and computational methods for Process and Energy Systems Engineering , focusing on integrated decision-making, performance optimization, and process intensification with industrial validation. Education: Ph.D., Chemical Engineering, University of Minnesota (2006) M.Sc., Interface Process Engineering, 'Babeş-Bolyai' University (2001) Diploma, Chemical Engineering, 'Babeş-Bolyai' University (2000) Research Thrusts: Integrated decision-making in chemical/energy supply chains Process performance monitoring and optimization Process integration and intensification Key applications include grid-responsive chemical plants, intensified distillation/column designs, and renewable energy integration for building systems. Scientific Awards: Frank A. Liddell, Jr. Fellowship NSF CAREER Award (2015-2020) Moncrief Grand Challenges Faculty Award (2014) AIChE Outstanding Young Researcher Award (2017) Implementation : His group has translated research into commercial tools through partnerships with industrial test beds and is working to integrate methods into commercial simulators. They explore predictive approaches for building energy management and strategic capital investment analysis in next-generation energy systems.
Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.
Aleksander Kubica is an Assistant Professor of Applied Physics at Yale University, specializing in quantum information science with a focus on quantum error correction and fault tolerance. His research bridges quantum many-body physics and topological codes, particularly exploring applications in superconducting circuits and quantum architectures. He holds a Ph.D. from the California Institute of Technology and a B.S. from the University of Warsaw. Dr. Kubica's work addresses foundational challenges in scalable quantum computing, including optimizing error correction protocols, developing fault-tolerant architectures, and analyzing the intersection of quantum metrology with error mitigation. Recent contributions include advancements in erasure qubits, correlated noise decoding, and topological code adaptations. His research often involves interdisciplinary approaches, combining theoretical physics with algorithm design and hardware-efficient solutions. Key themes in his publications include improving error correction thresholds, designing low-overhead quantum architectures, and exploring novel decoding strategies for topological codes. While no specific awards are listed, his active research trajectory and contributions to quantum computing indicate significant scholarly engagement in the field.
Mithuna S. Thottethodi is a Professor and Interim Associate Head of Teaching and Learning at the Elmore Family School of Electrical and Computer Engineering at Purdue University. He holds a B.Tech. from the Indian Institute of Technology, Kharagpur (1996), and a Ph.D. in Computer Science from Duke University (2002). His research focuses on computer architecture, interconnection networks, distributed systems, and security, with notable work on sparse tensor accelerators and processing-near-memory architectures. His work has been funded by the NSF, AT&T, and SK Hynix. Research interests include security, interconnection networks in multicores, storage performance optimization, and memory hierarchies. Notable contributions span hardware accelerators for machine learning, secure speculative execution, and datacenter network congestion control. He has advised over 20 graduate students, many of whom have joined top tech firms like Google, Microsoft, and Intel. Awards: NSF CAREER Award (2007) Wilfred Hesselberth Teaching Excellence Award (2021) Multiple Eta Kappa Nu Outstanding Professor Awards Teaching includes undergraduate courses like EE 437 (Computer Design) and graduate courses such as ECE 666 (Advanced Computer Architecture). He also advises VIP and EPICS student teams.
Kyle C. Hale is an Associate Professor at Oregon State University's School of Electrical Engineering and Computer Science (College of Engineering). He holds a Ph.D. and M.S. from Northwestern University (2016, 2013) and a B.S. in Computer Science from UT Austin (2010). Prior to joining Oregon State in 2024, he served as an Associate Professor at Illinois Tech in Chicago. His research spans operating systems, high-performance computing (HPC), virtualization, computer architecture, and system security. Current work focuses on specialized system software stacks for emerging computing paradigms like memory disaggregation and parallelism optimization. He leads the HExSA Lab and collaborates with the HiPCastor group. Scientific Awards: NSF CAREER Award (2023-2028) Illinois Tech College of Computing Excellence in Research (2023) Illinois Tech College of Computing Excellence in Teaching (2021) Illinois Tech Department of Computer Science Teacher of the Year (2020) EuroSys '22 Best Artifact Award Recent Research Trends: His publications emphasize compiler techniques for memory-disaggregated systems, optimizing parallel runtimes through hardware-software integration, virtualization at fine granularities, and accelerating machine learning workloads via system-level innovations. Keywords include HPC, virtualization, parallelism, and secure execution contexts. Teaching: Courses taught include Computer Architecture (CS/ECE 472), System Security (CSP 544), Operating Systems (CS 450), and advanced topics in serverless/edge computing. He actively recruits PhD students to the HExSA Lab.
Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.
Henry Hoffmann is a Professor and Liew Family Chair in the Department of Computer Science at the University of Chicago. His research focuses on self-aware computing systems that adapt to meet goals like power efficiency, performance, and security. He leads the SEEC project and has contributed to advancements in computer architecture, embedded systems, and quantum computing. Hoffmann received the PECASE (2019), DOE Early Career Award (2015), and was inducted into the Samsung Hall of Fame for discovering vulnerabilities in SmartTVs. He holds a PhD from MIT (2013) and has co-founded Config Dynamics (2019). His work bridges control theory, machine learning, and traditional computer systems to create adaptive solutions for modern computing challenges. Education: PhD in Electrical Engineering and Computer Science from MIT (2013), SM (2003), and B.S. (1999) with highest honors from UNC Chapel Hill. Professional experience includes roles at Tilera Corporation and MIT Lincoln Laboratory. Research Interests: Self-aware systems, adaptive resource management, quantum computing optimization, and cybersecurity. His SEEC framework enables systems to autonomously adapt to constraints like energy and performance. Recent work explores applying adaptive techniques to AI/ML models for energy-efficient inference and security. Awards: Over $19M in research funding, 100+ publications, and leadership roles in NSF Expedition EPiQC (quantum computing). Named Chair of UChicago CS Department (2023-2024). Labs/Teams: Systems Group, EPiQC (quantum computing), and CERES (unstoppable computing systems). Current students include Jerry Ding and Ryien Hosseini. Notable alumni include Yi Ding (now faculty at Purdue) and Nikita Mishra.
Mehmet Esat Belviranli is an Assistant Professor in the Computer Science Department at the Colorado School of Mines, where he directs the High Performance Systems and Software Lab (HyperSys). His research focuses on increasing resource utilization in heterogeneous architectures through runtime systems, scheduling algorithms, and performance modeling, with publications in top venues including MICRO, PPoPP, and SC. Education: Ph.D. in Computer Science, University of California, Riverside (2016) M.S. in Computer Science, Bilkent University (2009) B.S. in Computer Science, Bilkent University (2006) Belviranli's research spans heterogeneous architectures, runtime systems, performance modeling, parallel programming, autonomous computing, deep learning acceleration, cyber-physical systems, and edge-cloud platforms. His work develops analytical models and programming abstractions to address resource management, scheduling, and security challenges in diversely heterogeneous systems, with applications in edge computing, autonomous systems, and machine learning acceleration. Recent projects emphasize real-world constraints and security implications. His publication trends reveal increasing focus on edge-cloud resource management (e.g., HARNESS), security vulnerabilities in heterogeneous systems (e.g., MC3), and deep learning acceleration under resource constraints. Key themes include memory contention modeling, scheduling for cyber-physical systems, and concurrent DNN execution, reflecting a shift toward practical deployment in security-sensitive edge environments. Scientific Awards: U.S. Air Force Research Lab Summer Faculty Fellowship Award (2022) U.S. Air Force Research Lab Summer Faculty Fellowship Award (2021) Oak Ridge National Laboratory Significant Event Award (2019) Best Paper Finalist, IEEE HPEC 2018 Outstanding Paper Award, DATE 2024 Belviranli mentors Ph.D. students Ismet Dagli (MLCommons Rising Star 2024, CGO'24 SRC finalist) and Justin Davis (DATE'24 Outstanding Paper Award winner). He has secured $2M+ in funding from NSF, DoE, and SRC, including an NSF-SaTC grant on mobile security (2024), a DoE grant on superconductive systems (2023), and an NSF FuSe grant on graphene nanoribbons (2023), often leading multi-institutional teams from Rochester, Virginia, Arizona, and Minnesota. The HyperSys Lab develops ecosystems for high-performance heterogeneous systems, with recent projects including HARNESS for edge-cloud resource management and MC3 for mobile SoC security. The lab has received equipment donations from Google Coral.ai and Xilinx, and collaborates with national labs on security challenges and next-generation semiconductor technologies.
Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.
Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.
Kenneth Ross is a Professor in the Computer Science Department at Columbia University in New York City. His primary appointment is within the Department of Computer Science, with affiliations including the Foundations of Data Science Committee. His work bridges theoretical database research and practical system implementation. His research focuses on database systems with particular expertise in query processing, query language design, data warehousing, and architecture-sensitive database system design. Additional research spans computational biology, especially analysis of large genomic data sets. Current projects include Linear Algebra Operators in Databases for machine learning workloads and Repeats and Somatic Mutation analysis in genomics. His work consistently addresses the intersection of hardware capabilities and database system design. Ross leads the Database Research Lab at Columbia, which has produced significant work on query optimization, GPU database processing, and hardware-conscious database systems. His recent publications demonstrate strong focus on adapting database systems to modern hardware including GPUs, SIMD processors, and persistent memory. His scientific recognition includes: Packard Foundation Fellowship Sloan Foundation Fellowship NSF Young Investigator Award Distinguished Faculty Teaching Award (2008) Ross actively advises undergraduate engineering students (juniors with last names P-Z) and has taught foundational courses including Introduction to Databases and Programming and Problem Solving for over two decades. His teaching portfolio shows consistent engagement with both theoretical concepts and practical implementation challenges in computer science education.
Jiaxin Lin is an Assistant Professor in the Department of Electrical and Computer Engineering at Cornell University , affiliated with the Computer Systems Laboratory . She earned her Ph.D. in Computer Science from UT Austin (2025) , preceded by an M.S. from University of Wisconsin-Madison and a B.S. from ShenYuan Honors College at Beihang University. Her research focuses on co-designing software and hardware systems to enable high-performance data center communication, particularly through: Programmable network interface controllers (SmartNICs) Terabit network system stacks Cache/memory interconnects Compilers for in-network computing Chip-to-chip interconnects Her work addresses challenges in portability across heterogeneous SmartNICs, demonstrated through the development of the Alkali compiler framework (NSDI '25). Key themes include hardware abstraction, data center scalability, and network-compute co-design. Scientific Awards: Google Junior Faculty Award (2025) MIT EECS Rising Star (2024) Google Ph.D. Fellowship (2021) Meta Ph.D. Fellowship (2021)
