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Chang Hyun Park is an Assistant Professor at the Department of Information Technology, Uppsala University, where he is part of the Uppsala Architecture Research Team. His research focuses on computer architecture with emphasis on memory systems, virtualization, and system software optimization. Dr. Park completed his doctoral studies at KAIST (Korea Advanced Institute of Science and Technology) in South Korea, where he was advised by Professor Jaehyuk Huh. Prior to his current position, he served as a post-doctoral researcher at Uppsala University working with Professor David Black-Schaffer. Dr. Park's research spans several critical areas in computer architecture and systems: Virtual memory systems and address translation mechanisms Cache hierarchy optimization and memory systems design Support for non-volatile memory and heterogeneous memory systems Virtualization technology and optimizations for cloud environments High-speed I/O device integration and accelerator support His publication record demonstrates a consistent focus on improving memory system performance, particularly in virtualized environments. Over the past decade, his work has evolved from fundamental virtual memory optimizations to addressing challenges in emerging memory technologies and large-scale system architectures. Recent publications show increasing emphasis on heterogeneous memory systems, graph processing workloads, and hardware-software co-design approaches. Dr. Park actively collaborates with researchers at Uppsala University, particularly with Professor David Black-Schaffer, and maintains connections with his alma mater KAIST. His work appears regularly in top-tier computer architecture conferences including ISCA, MICRO, ASPLOS, and MEMSYS.

• Virtual Memory Systems
• Address Translation
• Cache Hierarchy
• +7 more

Ioannis Sourdis is a Full Professor at the Department of Computer Engineering, Chalmers University of Technology, Sweden. His research focuses on computer architecture, reconfigurable computing, network-on-chip (NoC) design, memory systems, and fault-tolerant embedded systems, with applications in biomedical informatics and hardware security. Current projects include EUMMSS (Efficient Uncore Mechanisms for Multicore Space Systems, funded by the Swedish National Space Board) and eProcessor (European Processor Ecosystem, funded by the European Commission). Past initiatives include the DeSyRe project (on-demand system reliability), ECOSCALE (exascale reconfigurable computing), and SHARCS (secure hardware-software architectures). His work spans NoC router design (e.g., FastTrackNoC, DDRNoC), memory compression (MemSZ, L2C), and biomedical security applications (heartbeat-based protocols). He has published extensively in venues like DATE, ICS, PACT, and IEEE Transactions on Networking. Key research areas: Chiplet-based systems , hybrid memory architectures , FPGA acceleration , and real-time stream aggregation .

• Computer Architecture
• Reconfigurable Computing
• Network-on-Chip (NoC)
• +7 more

Professor Per Stenström is affiliated with the Department of Computer Science and Engineering at Chalmers University of Technology . His research focuses on computer architecture , memory systems optimization , and energy-efficient computing , with significant contributions to DNN accelerator design and cache management . Research Trends : His recent publications emphasize Memory compression techniques for energy efficiency Hardware-software co-design for DNN acceleration Security in microarchitectural optimizations Hybrid memory systems for near-memory computing These works span both theoretical and applied aspects of computer architecture, with a particular focus on data redundancy elimination , parallel processing , and quality-of-service constraints . His work has influenced the development of energy-aware resource management frameworks and resilient EU HPC systems , as evidenced by his long-standing contributions to the field since the early 2010s.

• Computer Architecture
• Memory Systems Optimization
• Energy-Efficient Computing
• +3 more

David Black-Schaffer is a Professor at Uppsala University's Department of Information Technology, specializing in computer systems research. As of 2023, he serves as Dean of Research for the Faculty of Science and Technology. His work bridges software and hardware innovations to enhance data movement efficiency in computer systems, with applications commercialized through a startup and integrated into industry standards like OpenCL. Black-Schaffer earned his PhD in Electrical Engineering from Stanford University in 2008, focusing on many-core processor programming. His career spans roles at Apple Inc. (contributing to OpenCL standards), postdoctoral research at Uppsala University, and academic progression from assistant to full professor (2010–2017). He has held leadership roles including Head of the Division of Computer Systems (2022) and department representative on the faculty Advisory Committee for Research (2021). His research spans computer architecture, memory systems, parallel programming, and simulation techniques. Recent publications (2024–2020) explore garbage collection, cache optimization, memory contention, NUMA systems, and instruction scheduling. Key trends include software-hardware co-design for power efficiency, reuse-aware data placement, and machine learning for performance modeling. Knut & Alice Wallenberg Foundation: Wallenberg Academy Fellowship Prolongation (2020–2025), Wallenberg Academy Fellow (2016–2021) Swedish Research Council (VR): Project Grant (2019–2024), Young Researcher Grant (2015–2018), Framework Grant (2012–2017) European Research Council: ERC Starting Grant (2017–2022) Teaching Awards: Uppsala Engineering and Science Student Union Pedagogical Prize (2012), Uppsala University Pedagogical Prize (2016), Uppsala Technical Physics Students' Teaching Award (2019) Other Grants: ScalableLearning flipped classroom project (2012–2020), Arm Ltd. collaborations on memory system designs He pioneered flipped-classroom teaching through the ScalableLearning project, impacting over 80,000 students. His research is conducted in collaboration with institutions like Arm Ltd., with past contributions to Apple's OpenCL implementation and UPMARC research center.

• Computer Architecture
• Memory Systems
• Parallel Programming
• +4 more

Lars Karlsson is an Associate Professor at the Department of Computing Science, Umeå University, where he serves as Assistant Head of Department with responsibilities for undergraduate education. His research focuses on developing efficient algorithms for matrix and tensor computations within high-performance computing environments. He is affiliated with the Parallel and Scientific Computing research group at Umeå. Karlsson's primary research areas include: Numerical Linear Algebra : Specializing in matrix factorizations and eigenvalue computations Parallel Algorithms : Designing scalable solutions for distributed and shared-memory systems Tensor Computations : Developing decomposition methods and completion algorithms Performance Optimization : Auto-tuning techniques for modern computing architectures His publications (2010-2025) demonstrate consistent focus on parallel algorithms for numerical problems, particularly matrix reductions, eigenvalue computations, and tensor decompositions. Recent work emphasizes auto-tuning, robustness in numerical methods, and efficient scheduling for high-performance systems. The majority of publications involve collaborative research within European computing consortia like NLAFET. Karlsson contributes to educational research, having explored mastery learning approaches in university settings. His administrative responsibilities include oversight of undergraduate programs at the Department of Computing Science.

• High-Performance Computing
• Numerical Linear Algebra
• Parallel Algorithms
• +2 more

Jan Carlson is a Professor at Mälardalen University's School of Innovation, Design and Engineering, specializing in the Division of Computer Science and Software Engineering. His primary focus is on software engineering, particularly model-based and component-based development of embedded systems. He earned his M.Sc. from Linköping University (2000) and a doctoral degree from Mälardalen University (2007) with a thesis on event pattern detection for embedded systems. Research interests include allocation optimization, timing analysis, code generation, real-time systems, and safety-critical component reuse. His work often addresses challenges such as cache-aware response time analysis, limited preemption scheduling, and integration of GPU components in embedded systems. He has contributed to projects like SCALL (a component allocator for heterogeneous systems) and Rubus (a GPU-aware component model). His research also explores continuous integration practices in model-based development and decision support systems for component selection. Key contributions include studies on architectural change management, ontology development for systems of systems, and tools for consistency checking between system models and implementations. He has authored over 80 publications, with recent work focusing on performance prediction, resource utilization, and safety-critical system integration. No notable awards are mentioned, though his extensive publication record highlights significant academic impact. Jan Carlson has advised numerous students and research teams but no explicit student names are listed in the provided text. His work is closely tied to industrial collaboration, addressing real-world challenges in automotive, railway, and smart industry domains. He actively participates in workshops and conferences, such as MARCH and ModComp, to advance model-driven engineering practices.

• Software Engineering
• Embedded Systems
• Model-Based Development
• +5 more

Per Stenstrom is a Professor of Computer Engineering at Chalmers University of Technology, Sweden since 1995. His research focuses on computer architecture, particularly high-performance memory systems and energy-efficient computing. He has authored/co-authored four textbooks, over 200 publications, 20 patents, and supervised approximately 25 PhD students. Awarded ACM Fellow and IEEE Fellow. Member of Academia Europaea and the Royal Swedish Academy of Engineering Sciences. Co-founder of the HiPEAC Network of Excellence. Served as Editor or Associate Editor for journals like ACM Transactions on Architecture and Code Optimization and IEEE Transactions on Computers . Program Chair for major conferences including ISCA, HPCA, IPDPS, and ACM International Conference on Supercomputing. His research innovations include cache compression techniques, memory optimization strategies, and energy-aware resource management in multicore systems. Ongoing work emphasizes secure and scalable cache partitioning, hybrid memory systems, and defense mechanisms against microarchitectural attacks.

• Computer Architecture
• High-Performance Computing
• Memory Systems
• +3 more