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Geoffrey NelissenView profile

Assistant Professor

• Real-Time Systems
• Schedulability Analysis
• Multicore Platforms
• +3 more

Geoffrey Nelissen is an Assistant Professor in the Department of Mathematics and Computer Science at Eindhoven University of Technology. He holds additional roles as a Research Scientist and Investigador Auxiliar at INESC TEC (Portugal), contributing to interdisciplinary research in real-time systems. His work focuses on schedulability analysis, parallel task execution, and real-time communication protocols, with applications in embedded systems and multicore architectures. Research Interests: Real-Time Scheduling Response Time Analysis Multi-core and Parallel Systems Time-Sensitive Networking (TSN) Formal Verification Recent work emphasizes schedule abstraction frameworks, memory contention analysis, and deterministic communication protocols. His research has received recognition through multiple best paper awards including ICESS 2021 and RTAS 2022. He actively contributes to conferences like RTSS and ECRTS while teaching courses on Real-Time Systems and Operating Systems. Collaborations span European institutions with focus on embedded systems, autonomous driving, and safety-critical applications. Current projects explore holistic approaches to WCRT analysis and resilient real-time communication architectures.

• VHDL hardware synthesis
• Novel Microprocessor Architectures
• Stack-based processors
• +3 more

Christopher Crispin-Bailey is a Senior Lecturer in the Department of Computer Science at the University of York. He holds a BEng and PhD from Teesside University. His research focuses on VHDL hardware synthesis, novel microprocessor architectures, stack-based processors, optimization of stack-oriented object code, multimedia server architectures, and bus arbitration methods. Career highlights include roles as a Teaching Research Fellow (1996–1997), Senior Lecturer at the University of Teesside (1997–1999), and Lecturer at the University of York since 1999. He currently holds the title of Senior Lecturer and is part of the Real-Time and Distributed Systems research group. His contributions span hardware design, embedded systems, and biomedical signal processing. He contributes to departmental roles as an Exam Paper Checker and Union Rep. His work emphasizes practical applications in both academic and industry contexts, with a focus on optimizing hardware and software systems for efficiency and scalability.

• Real-Time Systems
• Operating Systems
• Multiprocessor Architectures
• +3 more

Cláudio Maia is a Lecturer and Integrated PhD Researcher at the Department of Electrical and Computer Engineering, University of Porto, Portugal. He holds a BSc and MSc in Computer Engineering from the School of Engineering, Polytechnic Institute of Porto, and a PhD in Electrical and Computer Engineering from the University of Porto (2018). His research focuses on real-time operating systems, hypervisors, multiprocessor architectures, and real-time scheduling theory, particularly addressing challenges in parallel task scheduling and resource contention in multicore platforms. Education: Bachelor’s Degree (B.Sc.) in Computer Engineering, School of Engineering, Polytechnic Institute of Porto Master’s Degree (M.Sc.) in Computer Engineering, School of Engineering, Polytechnic Institute of Porto PhD in Electrical and Computer Engineering, University of Porto (2018) Research interests include real-time systems, multiprocessor scheduling theory, and embedded systems. He has contributed to the development of scheduling models such as the AER execution model and semi-partitioned scheduling with work-stealing for fork-join tasks. His work addresses interference mitigation in shared-resource environments and WCRT (Worst-Case Response Time) analysis for parallel real-time tasks. Cláudio has participated in numerous conferences and workshops, including ETFA, RTNS, and CPS Week, where he has presented research and served on program committees. He has also delivered seminars on topics like work-stealing dynamics and parallel task scheduling in real-time systems. His research is affiliated with the CISTER Research Centre, focusing on embedded and real-time systems. Key technical contributions include improving schedulability analysis for the 3-phase task model, addressing bus contention in multiprocessor systems, and exploring WCRT bounds in multicore platforms. His work bridges theoretical scheduling models with practical implementations, emphasizing predictability and performance in real-time environments.

Christine RochangeView profile

Professor

• Real-Time Systems
• Worst-Case Execution Time (WCET) Analysis
• Timing Predictability
• +3 more

Christine Rochange is a Professor at the University of Toulouse, affiliated with the IRIT research lab and the TRACES research group. Her work focuses on worst-case execution time (WCET) analysis for hard real-time systems, timing predictability in parallel architectures, and time-aware hardware design. She coordinates major projects such as TOAST (a French initiative for time-oriented critical systems) and leads the TACLe project's Working Group 1 on timing models. Her research addresses challenges in multi-core WCET analysis, synchronization overhead reduction, and mixed-critical systems. Key contributions include the OTAWA static WCET analysis toolset and foundational work on time-predictable architectures. She has supervised PhD students in areas like parallel real-time task scheduling and bus arbitration schemes. Rochange actively participates in program committees for conferences like ECRTS and RTAS, and teaches courses on computer architecture, parallel programming, and real-time systems at Université Paul Sabatier. Her recent articles explore formal verification of processor pipelines, timing predictability in GPUs, and hardware-software co-design for embedded AI applications. She has coordinated international collaborations through projects like parMERASA (EU FP7) and W-SEPT (ANR), advancing the state-of-the-art in real-time systems predictability.