Find Academic Supervisors

• Process Technology
• Device Design
• Silicon Carbide (SiC) Electronics
• +3 more

Carl-Mikael Zetterling is a Professor and Head of Department at Kungliga Tekniska Högskolan (KTH) in Stockholm, Sweden, affiliated with the School of Electrical Engineering and Computer Science (ICT) and the Electronics and Embedded Systems department. His research focuses on process technology and device design for high-temperature, high-power silicon carbide (SiC) electronics, expanding into SiC-based analog and integrated circuits. He has authored over 300 publications, including books on SiC process technology and plagiarism prevention. Dr. Zetterling has held leadership roles such as Vice Dean of the School of ICT (2013–2017) and teacher representative on KTH's faculty board. He has collaborated internationally at Stanford University, Kyoto University, and Kyoto Institute of Technology. His work addresses applications in extreme environments, including Venus exploration and fusion reactor monitoring, with a focus on radiation tolerance and thermal resilience. The 15 most recent publications highlight trends in wide bandgap semiconductors, gamma irradiation effects on SiC devices, and high-temperature integrated circuits. His articles span structural health monitoring with machine learning, novel SiC diode designs, and radiation-hardened electronics. Key contributions include advancements in self-aligned contacts, trench MOSFETs, and compact modeling for extreme conditions. While no formal awards are listed, his roles in technical program committees (TMS Electronic Materials Conference, IEEE SISC Conference) and editorial work demonstrate significant academic service. He teaches courses ranging from digital design to high-temperature electronics, overseeing degree projects in embedded systems, communication, and nanotechnology.

• VLSI Testing
• Circuit Design
• Test Compaction
• +7 more

Irith Pomeranz is the Cadence Professor of Electrical and Computer Engineering at Purdue University's College of Engineering. Her research focuses on advanced testing methodologies for VLSI circuits, including functional test compaction, fault diagnosis, and built-in self-test (BIST) techniques. She is affiliated with the Department of Electrical and Computer Engineering and has contributed extensively to improving test efficiency and fault coverage in digital circuits. Her work addresses challenges such as aging effects, transition faults, and path delay faults, with a particular emphasis on practical implementations for industrial applications. Key areas of interest include modular test sequences, configuration-based compaction, and dynamic testing strategies for in-field environments. She has developed algorithms for dual-target diagnostic testing and synchronization mechanisms for online fault detection in logic blocks. Research Trends in her publications emphasize innovations like storage-based BIST schemes, adaptive test scheduling, and shared test data architectures. These advancements aim to reduce test data volume, improve fault coverage, and enhance reliability in modern integrated circuits. Her work often bridges theoretical foundations and practical hardware implementations. Grants & Advising : While specific grants or student advisees are not listed, her prolific publication record indicates active involvement in research projects and graduate supervision within Purdue's ECE department. Labs & Teams : Her contributions are likely tied to Purdue's VLSI and testing research groups, though specific lab affiliations are not detailed in the provided text.

Xuming HeView profile

Associate Professor

• Computer Vision
• Machine Learning
• Artificial Intelligence
• +9 more

Xuming He is an Associate Professor at the School of Information Science and Technology (SIST), ShanghaiTech University, where he leads the PLUS Lab. His research spans computer vision and machine learning with a focus on developing algorithms that operate effectively under limited supervision and evolving data conditions. His core research interests include weakly-supervised and few-shot learning for scenarios with sparse annotations, continual learning frameworks for knowledge retention during sequential task acquisition, semantic segmentation techniques for scene understanding, and multimodal vision-language representations. He emphasizes interpretable machine learning to build transparent AI systems capable of human-understandable reasoning, addressing critical challenges in model trustworthiness and deployment reliability. Recent publications reveal strong trends toward novel class discovery in long-tailed recognition scenarios, physics-informed generative modeling for scientific applications, and robust segmentation under distribution shifts. His work increasingly integrates large language models for multimodal reasoning while maintaining focus on efficiency in resource-constrained environments like robotic grasping and medical imaging analysis. He actively mentors students, having supervised Qian He to PhD completion and Chuanyang Hu to Master's degree in 2023. He welcomes prospective graduate students through ShanghaiTech's Computer Science & Technology program and offers undergraduate research projects requiring minimum six-month commitments. The PLUS Lab under his direction drives innovation in learning under supervision constraints, with recent work spanning medical tumor analysis, cross-view geolocation, photonic computing, and semiconductor design verification. The lab's research bridges theoretical advances with practical applications across healthcare, robotics, and scientific discovery domains.

Thuy T. LeView profile

Professor

• Digital System Design
• Computer Architecture
• Hardware Accelerators
• +6 more

Thuy T. Le is a Professor of Electrical Engineering at San Jose State University's College of Engineering. With a distinguished career spanning several decades, he teaches graduate and undergraduate courses in digital system design, computer architecture, microprocessor systems, and related fields. His academic journey began with earning B.S., M.S., and Ph.D. degrees from the University of California, Berkeley. Professor Le's research interests encompass a broad spectrum of cutting-edge technological domains. His primary focus areas include System-on-Chip (SoC) and Embedded System Design, Hardware Accelerators for complex algorithms, Quantum Computing, implementation of Probability theory and Monte Carlo simulation, and radiation effects on electronic devices and systems. His work bridges traditional electrical engineering with emerging computational paradigms, demonstrating a consistent ability to adapt to evolving technological landscapes while maintaining strong foundations in core engineering principles. Analysis of Professor Le's publication record reveals a consistent trajectory from nuclear reactor physics and computational methods toward modern hardware acceleration and quantum computing. His early work focused on nuclear reactor simulation and radiation shielding, then evolved to parallel computing and distributed systems, and has recently centered on hardware acceleration for complex algorithms, quantum computing applications, and AI hardware. This progression demonstrates his ability to transition between major technological paradigms while maintaining expertise in computational methods and hardware implementation. Professor Le has demonstrated significant leadership in professional service, having served as keynote speaker, general chair, technical program chair, session chair, reviewer, and committee member for numerous international conferences. His service extends beyond academia through his role as Co-Founder and Advisor of the Vietnamese Strategic Ventures Network and Chairman of the Board of the United States–Vietnam Foundation. In his educational role, Professor Le has made substantial contributions to engineering curriculum development and assessment. He has taught a wide range of courses including EE271 (Advanced Digital System Design), EE210, EE250, and various project/thesis courses. His research advising spans digital system design, ASIC, SOC, and hardware accelerators. He has also collaborated with local companies on projects related to high-performance system architectures, parallel algorithms, digital arithmetic, and System-on-Chip verification.

• Testability
• Built-in Self Test (BIST)
• Digital Circuit Testing
• +3 more

Professor Jacob Savir is a distinguished academic in the Department of Electrical and Computer Engineering at the New Jersey Institute of Technology . He specializes in testability, built-in self-test (BIST), and fault detection for digital and analog circuits. His work focuses on improving integrated circuit testing methodologies, including BIST pretesting, defect level analysis, and reliability optimization in safety-critical systems. His research interests span BIST architectures, delay fault analysis, analog circuit testing, and power-constrained test synthesis . He has contributed extensively to the development of testing algorithms for embedded memories, scan designs, and fault diagnosis in complex systems. Notable contributions include studies on the impact of BIST pretesting on IC defect levels and yield optimization. His work bridges theoretical advancements with practical applications in aerospace and industrial electronics. Despite no awards listed, his substantial citation count (1,897) and h-index (22) reflect his influential contributions to the field. Prof. Savir has collaborated on 114 research outputs since 1977, with a focus on enhancing circuit testability and reliability across domains like FPGA-based systems and embedded memory diagnostics. His research emphasizes both academic rigor and industrial relevance, addressing challenges in modern VLSI design and testing.

Azadeh DavoodiView profile

Professor

• Electronic Design Automation (EDA)
• Integrated Circuit Design
• Machine Learning in Hardware
• +5 more

Azadeh Davoodi is a Vilas Distinguished Achievement Professor and Associate Chair of Undergraduate Studies in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. Her research focuses on Electronic Design Automation (EDA), integrated circuit debug, and machine learning applications in VLSI design. She holds editorial roles in journals like IEEE TCAD and ACM TRETS, and has chaired major conferences such as ISPD 2015 and served on technical program committees for DAC, ICCAD, and others. Education: PhD in Electrical Engineering, University of Maryland-College Park (2006) Research Interests: Machine learning for VLSI chip design VLSI design automation for machine learning IC-CAD for emerging nanotechnologies Hardware security Recent Research Trends: Her work bridges machine learning and hardware design, with publications on neural network optimization, distributed inference, and explainable AI for circuit design. She emphasizes energy-efficient CNNs, latency reduction in edge computing, and security in split manufacturing. Awards: 2025 DATE Best Paper Candidate 2024 Vilas Distinguished Achievement Professor 2015 ACM Best Paper Award 2011 NSF CAREER Award Service and Grants: Leads NSF-funded projects on explainable ML for CAD and holds grants for distributed neural network synthesis. Her service includes roles as IEEE HKN member and editorial board positions. Labs/Teams: Engages in interdisciplinary research teams at UW-Madison, focusing on EDA innovation and hardware-software co-design.

• VLSI Design
• Built-In Self-Test (BIST)
• Test Data Compression
• +7 more

Chr. Kavousianos is an Assistant Professor in the Department of Informatics at the University of Ioannina, Greece. He is actively engaged in research and teaching in the fields of VLSI design, testability, and low-power testing. He has been involved in major national and international research programs such as Heracleitus II, Pythagoras, and NSF-SRC (USA). Research Interests: His research focuses on advanced techniques in built-in self-test (BIST), test data compression, scan-based testing, fault tolerance, and embedded control architectures. He explores methods to reduce test data volume, power consumption during testing, and improve defect coverage in integrated circuits. Publication Trends: His recent publications (2004–2011) show a strong trend toward defect-aware testing, power-efficient test compression, and multicore SoC testing. He frequently collaborates with leading researchers, including Prof. Krishnendu Chakrabarty (Duke University). His work on multilevel Huffman coding and reseeding techniques has been highly influential, with one paper among the most accessed in 2004. Special Distinction for Excellent Academic Performance from TEE, 1996 Doctoral Scholarship 'In Memory of Professor Maritsa', 1999 Postdoctoral Scholarship from IKY, 2002 Advising and Grants: He has supervised multiple postdoctoral researchers, PhD candidates (e.g., Vasilis Tenentes, Emmanouil Kalligeros), and master’s students. He has led research projects such as 'Embedded Control Architectures' (Heracleitus II) and 'Design Techniques for Embedded Self-Control Circuits' (Pythagoras II). His international collaboration with Duke University included a postdoctoral research role in 2009. Labs and Teams: He leads a research group at the University of Ioannina with postdocs, PhD students, and visiting professors, including Prof. Krishnendu Chakrabarty. His team works on cutting-edge VLSI testing and design methodologies.

Marc ReichenbachView profile

Professor

• Integrated Circuits
• Embedded Systems
• VLSI Design
• +7 more

Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.

• Channel decoders
• Circuits for communications
• Cryptography
• +8 more

Guido Masera is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, where he has been actively involved in teaching and research for over two decades. He serves as a Member of the Board of Directors, Member of the GEDI Observatory for Gender Equality, Diversity and Inclusion, and Member of the Permanent University Observatory for monitoring the academic supply chain. His research interests span across channel decoders, circuits for communications, cryptography, deep learning, digital integrated circuits, field programmable gate arrays (FPGA), and hardware design. His work focuses on VLSI architectures for image and video coding, digital architectures for error correcting codes, application specific approximate computing, VLSI architectures for machine learning, digital architectures for bio-inspired processing, digital architectures for post-quantum cryptography, bio-inspired electronics for robotics and biomedical applications, RISC-V extensions and hardware accelerators, and circuit architectures for efficient machine learning and artificial intelligence. His recent publications (2025) demonstrate a strong focus on RISC-V architecture, particularly in the context of cryptographic implementations, hardware security, and post-quantum cryptography. His research group VLSILAB is actively engaged in cutting-edge research in hardware security, efficient processor design, and specialized computing architectures. Among his notable recognitions are the Premio Francesco Carassa awarded by the Telecommunications and Information Technologies Group Association (gtti) in 2010, and his recognition as a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) since 2007. He also serves as an Associate Editor for several prestigious journals including ELECTRONICS (2019-present), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (2015-2019), and IET CIRCUITS, DEVICES & SYSTEMS (2013-2016). Professor Masera has advised numerous PhD students working on advanced topics in VLSI design, post-quantum cryptography, hardware accelerators, and machine learning implementations. His current research projects include ISOLDE (2023-2026) and TRISTAN (2022-2025), both EU-funded projects focused on RISC-V technology and domain-specific ecosystems. He leads the VLSILAB research group at the Department of Electronics and Telecommunications, which focuses on cutting-edge research in VLSI architectures, hardware security, and specialized computing systems. The group collaborates with industry partners and participates in major European research initiatives.

Tsung-Yi HoView profile

Professor

• Design Automation for Microfluidic Biochips
• Nanometer Integrated Circuits
• Embedded Systems
• +3 more

Tsung-Yi Ho is a Professor in the Department of Computer Science at National Tsing Hua University, Taiwan. He holds the Hans Fischer Fellowship at the Technical University of Munich's Institute for Advanced Study (TUM-IAS). His primary research focuses on design automation for microfluidic biochips and nanometer integrated circuits, emphasizing reliability, optimization, and interdisciplinary applications in bioengineering. Ho received his Ph.D. in Electrical Engineering from National Taiwan University in 2005. He has held positions at National Cheng Kung University and National Chiao Tung University before joining National Tsing Hua University. His work bridges algorithmic design with practical biochip fabrication, addressing challenges like contamination control, routing optimization, and fault tolerance in microfluidic systems. His research interests span design automation for emerging technologies, including paper-based biochips and 3D microfluidic architectures. He has pioneered methods for integrating hardware-software co-design principles into biochip development, enhancing both functionality and reliability. His contributions include novel routing algorithms, contamination mitigation techniques, and reliability-aware synthesis frameworks. Ho has authored over 100 publications, including influential papers in IEEE Transactions on CAD and ACM journals. He serves on the editorial boards of multiple top-tier journals and chairs professional chapters for ACM and IEEE. His awards include the Humboldt Research Fellowship, Dr. Wu Ta-You Memorial Award, and Best Paper Awards at VLSI Test Symposium and IEEE Transactions on CAD. His current projects involve optimizing control-fluidic co-design for paper-based biochips and developing AI-driven frameworks for microfluidic functionality prediction. He collaborates widely, leading cross-disciplinary initiatives at TUM-IAS and Taiwan's academic institutions.

Luca BeniniView profile

Professor

• Embedded Systems
• Low Power Design
• System-on-Chip
• +7 more

Luca Benini is a Full Professor of Electronics at the University of Bologna's Department of Electrical, Computer and Systems Engineering. He also holds a Visiting Faculty Position at the Ecole Polytechnique Federale de Lausanne (EPFL) and serves as Chief Architect of the Platform 2012 project at STMicroelectronics in Grenoble, France. His educational background includes academic positions progressing from Assistant Professor (1998) to Associate Professor (2001) and finally Full Professor (2006) at the University of Bologna. He has held significant industry positions including IC Architecture and CAD Engineer at Integrated Information Technology Inc. (1994), Senior Member of R&D Staff at Synopsys Inc. (1996), and Visiting Researcher at Hewlett Packard Laboratories (1997-2004). Professor Benini's research focuses on designing systems for ambient intelligence, spanning multi-processor systems-on-chip, networks on chip, and energy-efficient smart sensors and sensor networks. His work has expanded into biochips for biological molecule recognition, bioinformatics, and advanced algorithms for in-silico biology. His expertise in low-power design of integrated circuits and systems earned him IEEE Fellow status in 2007. He has received multiple honors including best paper awards at IEEE GLS-VLSI and the European Wireless Sensor Networks Conference (both 2008), with three of his papers featured in 'Design Automation and Test in Europe - The Most Influential Papers of 10 Years' (Springer 2008). IEEE Fellow (2007) for contributions to design technologies for low power design Member of ARTEMISIA Steering Board (elected twice) Member of European Design and Automation Association Main Board Member of MEDEA+ EDA roadmap committee Member of EC Advisory group on Computing Systems Benini has held significant leadership roles in the academic community, serving as General Chair of the IEEE/ACM Design Automation and Test in Europe Conference (2009), DATE Program Chair (2005), and Program Chair for multiple specialized symposia. He serves as associate editor for several prestigious journals including IEEE Transactions on Computer-Aided Design and ACM Transactions on Embedded Computing Systems, and has organized influential workshops like the Dagstuhl Seminar on Power-Aware Computing Systems.

Krishnendu ChakrabartyView profile

Professor

• Testing and Design-for-Testability of Integrated Circuits
• Digital Microfluidics
• Biochips
• +3 more

Krishnendu Chakrabarty is the John Cocke Distinguished Professor of Engineering and Professor of Computer Science at Duke University, chairing the Department of Electrical and Computer Engineering. His research focuses on integrated circuits testing, microfluidics, biochips, and cyberphysical systems. He holds honorary titles from institutions globally and has received over a dozen best-paper awards. Education: B.Tech from IIT Kharagpur (1990), M.S.E. and Ph.D. from University of Michigan (1992, 1995). Awards include Humboldt Research Award (2013), IEEE Computer Society Technical Achievement Award (2015), and AAAS Fellowship (2018). Research explores fault diagnosis in hardware, smart manufacturing, and biochip automation. His cyberphysical systems work includes hybrid microfluidic platforms for single-cell analysis and droplet-based bioassays. Collaborations with TUM-IAS focus on Microfluidic Design Automation (MDA). Editor-in-Chief of IEEE Transactions on VLSI Systems and former Editor of ACM Journal on Emerging Technologies. Active in academic leadership and interdisciplinary projects, emphasizing sustainability and advanced manufacturing.

Dong S. HaView profile

Professor

• Analog IC Design
• RF ICs
• Power Management Circuits
• +7 more

Dong S. Ha is a Professor in the Bradley Department of Electrical and Computer Engineering at Virginia Tech. As Founding Director of the Multifunctional Integrated Circuits & Systems (MICS) Lab, he focuses on advanced circuit design for energy harvesting, RF systems, and high-temperature electronics. His work spans analog/RF ICs, power management circuits, and wireless IoT solutions with machine learning integration. Education: PhD (1986) and MS (1984) in Electrical and Computer Engineering from the University of Iowa; B.S. (1974) in Electrical Engineering from Seoul National University. Research interests include energy harvesting (piezoelectric, thermal, RF), high-temperature RF circuits for oil/gas/spacecraft applications, and smart IoT systems. He actively seeks students for projects in RF design, energy harvesting, and embedded systems. His lab develops cutting-edge solutions for harsh environment communication, sustainable energy systems, and smart agriculture monitoring. Awarded IEEE Fellow (2008) for contributions to VLSI design/test. Key publications span energy harvesting circuits, GaN-based high-temperature systems, and low-power IoT architectures. Current projects include self-sustaining smart farm networks using federated learning and attack-resistant sensor systems. Labs/Teams: Leads MICS Lab focusing on integrated circuits and systems. Collaborates on cross-disciplinary projects involving machine learning, embedded systems, and sustainable energy. Active in industry partnerships for aerospace and automotive applications.

Linda KatehiView profile

Professor

• Microwave and Millimeter-Wave Circuits
• MEMS Devices
• Terahertz Applications
• +5 more

Linda Katehi is a Professor of Electrical & Computer Engineering and Materials Science & Engineering at Texas A&M University, holding the O'Donnell Foundation Chair II. She is a Member of the National Academy of Engineering and American Academy of Arts and Sciences. Her research focuses on advanced electromagnetic systems, MEMS devices, and embedded intelligent sensors. Katehi earned her Ph.D. in Electrical Engineering from UCLA (1984), with prior degrees from UCLA and the National Technical University of Athens. Education: Ph.D., Electrical Engineering, UCLA (1984) M.S., Electrical Engineering, UCLA (1981) B.S., Electrical and Mechanical Engineering, National Technical University of Athens (1977) Research Interests: Katehi pioneers innovations in microwave circuits, MEMS-based reconfigurable systems, terahertz technology, and neuromorphic sensors. Her work emphasizes integrating artificial intelligence into hardware for adaptive sensing platforms. Recent projects include flexible electronics, time-domain system analysis, and sustainability in urban infrastructure. Awards & Recognition: Ramo Simon Founder’s Award (2015) Charter Fellow, National Academy of Inventors (2013) Leading Women in STEM Award (2012) Rudy E. Henning Mentoring Award (IEEE, 2011) Lab & Teams: Directs the Intelligent Electromagnetic Sensors Lab (IEMSL), advancing embodied intelligence in electronics. Her team develops AI-embedded sensors and reconfigurable systems for applications in healthcare, communications, and environmental monitoring. Collaborates across disciplines to address global sustainability and equity challenges.

Mehdi SadiView profile

Assistant Professor

• Secure and Reliable System-on-Chip Design
• AI and Neuromorphic Hardware
• Safety-critical Hardware
• +2 more

Mehdi Sadi is an Assistant Professor of Electrical and Computer Engineering at Auburn University's College of Engineering. He holds a Ph.D. from the University of Florida, an M.S. from the University of California-Riverside, and a B.S. from Bangladesh University of Engineering and Technology. His research focuses on secure and reliable system-on-chip design, AI/ML-driven VLSI CAD/EDA, neuromorphic hardware, and emerging post-CMOS computing technologies. Notable achievements include earning the NSF CAREER Award for chiplet-based design optimization and a $175k NSF grant for magnetic RAM research. His work integrates machine learning with hardware co-design to enhance AI accelerators' performance, energy efficiency, and security. Recent projects include adversarial attack mitigation on AI hardware and reliability analysis of neuromorphic systems. Dr. Sadi's contributions span chiplet architecture, memory systems (e.g., STT-MRAM/SOT-MRAM), and fault-tolerant computing. He actively publishes on topics like skyrmion logic gates and TRNG implementations using MRAM. His work bridges theoretical machine learning advancements with practical hardware implementations, addressing critical challenges in next-generation computing systems.