Ningyuan Cao is an Assistant Professor in the Department of Electrical Engineering at the University of Notre Dame, College of Engineering. He leads the Circuit and System Intelligence Research Lab , focusing on the intersection of advanced hardware design and real-time/low-power machine learning applications. Education : Ph.D., Electrical and Electronics Engineering, Georgia Institute of Technology (2020) M.S., Electrical Engineering, Columbia University (2015) B.S., Electrical and Electronics Engineering, Shanghai Jiao Tong University (2013) His research investigates custom analog/mixed-signal circuits , digital architecture , and micro-system design for machine learning acceleration, distributed intelligence, and data-driven IC design automation. Key application domains include Internet-of-Everything, tactile internet, and mixed reality systems. Recent publications highlight work on Bayesian neural networks , privacy-preserving bio-signal encoders , transformer-based surrogate models , and compute-in-memory architectures . Technical themes span neuromorphic computing, uncertainty quantification, and hardware security.
Lisa Wills serves as Assistant Professor of Computer Science at Duke University's Trinity College of Arts & Sciences and holds a joint appointment in Electrical and Computer Engineering at the Pratt School of Engineering since 2019. Her research bridges computer architecture and domain-specific applications, with a focus on hardware acceleration for computationally intensive fields. Dr. Wills earned her Ph.D. from Columbia University in 2014. Her academic journey reflects a deep commitment to advancing hardware-software co-design methodologies for real-world computational challenges. Her research centers on developing efficient hardware accelerators for big data analytics, particularly in genomics, graph processing, and database systems. She pioneers frameworks that simplify accelerator deployment while tackling critical bottlenecks in genomic data analysis, protein structure prediction, and privacy-preserving computing. Current work focuses on hardware-aware machine learning systems and energy-efficient architectures for emerging AI applications. Analysis of her publication record reveals a clear trajectory: from foundational work in database processing units (2014-2016) to specialized genomic accelerators (2019-2021), then evolving toward ML-enhanced design automation (2022-2023) and cutting-edge architectural abstractions (2024-2025). Her research consistently targets the intersection of hardware efficiency and domain-specific computational demands, with increasing emphasis on AI/ML workloads. Google ML and Systems Junior Faculty Award (2025) Dr. Wills actively mentors doctoral students including Chris Kjellqvist (lead architect of Beethoven accelerator framework), Mason Ma (PyTFHE FHE framework), and Mansi Choudhary (COCOSSim accelerator simulator). Her research is supported by significant grants including the NSF AI Institute: Athena ($20M, 2021-2027), Meta-funded ProSE accelerator project (2023-2026), and NSF CAREER award (2021-2026), totaling over $25M in active funding. She directs the APEX Lab (Application-driven Programmable Efficient Accelerated Systems), which develops open-source frameworks like Beethoven for FPGA/ASIC accelerator deployment and focuses on lowering barriers for non-hardware researchers to leverage custom acceleration in genomics, AI, and big data applications.
Riad S. Wahby is an Assistant Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University's College of Engineering. His work focuses on designing secure hardware and software systems, with recent emphasis on cryptographic proof systems. He actively mentors PhD students and collaborates across disciplines in cybersecurity, blockchain, and formal verification. PhD in Computer Science, Stanford University MEng in Electrical Engineering, Massachusetts Institute of Technology SB in Electrical Engineering, Massachusetts Institute of Technology Wahby's research spans cryptography , blockchain security , zero-knowledge proofs , and secure hardware-software co-design . His work addresses challenges in verifiable computation, privacy-preserving protocols, and hardware subversion resistance. Recent publications reveal trends in zero-knowledge proof systems (SNARKs, MPC), blockchain security (anonymous blocklisting, decentralized auctions), and hardware-crypto integration (weird machines, verifiable ASICs). Technical focus areas include formal verification, side-channel analysis, and cryptographic compilers. Distinguished Student Paper Award, IEEE Symposium on Security and Privacy (Oakland16), 2016 Best Paper Award, USENIX Annual Technical Conference (ATC18), 2018 Wahby collaborates with researchers across institutions and industries, including Dan Boneh at Stanford, Mike Walfish at NYU, and Silicon Labs in industrial roles. His CyLab affiliations connect him to over $400K in seed funding opportunities and blockchain initiatives at CMU.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.
Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.
Swiss Federal Institute of Technology in LausanneSwitzerland
Andreas Peter Burg is a Tenured Associate Professor at the École Polytechnique Fédérale de Lausanne (EPFL), where he leads the Telecommunications Circuits Laboratory (TCL) within the School of Engineering. He holds multiple academic and administrative roles at EPFL including Associate Professor in Teaching (SEL, EDMI, EDEE), Director of SEL Management, and Member of the Doctoral Program Committee for Electrical Engineering. Dr. Burg received his Dipl.-Ing. degree in 2000 and Dr. sc. techn. degree in 2006 from ETH Zurich. His academic career includes positions as SNF Assistant Professor at ETH Zurich (2009-2011) before joining EPFL in January 2011 as a Tenure Track Assistant Professor, where he was promoted to Tenured Associate Professor in June 2018. His research focuses on circuits and systems for telecommunications , with particular expertise in silicon implementation of communication technologies, communication algorithms optimization for hardware, low-power VLSI signal processing, and digital integrated circuits. His work bridges theoretical communication concepts with practical circuit implementations, addressing challenges in wireless and wired communication systems. His recent publications (2024-2025) demonstrate a strong focus on next-generation communication technologies including 6G systems, advanced error correction coding, wireless sensing applications, and ultra-low power circuit design. These works span multiple subfields from LDPC and polar code decoding to RF signal processing and machine learning applications in wireless systems. Willi Studer Award (2000) ETH Medal for diploma thesis (2000) ETH Medal for Ph.D. dissertation (2006) Swiss National Science Foundation Assistant Professorship grant (2008) Dr. Burg has been involved in the development of more than 25 ASICs throughout his career and co-founded Celestrius, an ETH spinoff in MIMO wireless communication. His laboratory work focuses on practical implementations of communication algorithms with emphasis on power efficiency and hardware optimization. Current research directions include 6G technologies, wireless sensing applications, and novel error correction techniques for next-generation communication systems.
Giovanni De Micheli is a Professor of Electrical Engineering and Computer Science at EPF Lausanne, Switzerland. He also serves as Director of the Integrated Systems Centre and the Institute of Electrical Engineering at EPFL, and chairs the Scientific Committee of CSEM in Neuchatel. Previously, he held academic roles at Stanford University for 18 years, including Full Professor, Associate Professor, and Assistant Professor in the Department of Electrical Engineering. His research spans synthesis of digital circuits, hardware/software co-design, low-power design, and Networks on Chip (NoC) technology. 2003: IEEE Emanuel Piore Award 2000: Golden Jubilee Medal of the IEEE CAS Society 2000: ACM Fellow 1994: IEEE Fellow 1990: IEEE/CS Distinguished Service Award 1988: NSF Presidential Young Investigator Award His seminal contributions include pioneering C-based synthesis and Boolean matching algorithms for digital circuits, foundational work in dynamic power management using stochastic control, and the development of Network-on-Chip (NoC) technology. His publications, such as "Networks on Chips: A New SoC Paradigm" and "Dynamic Power Management for Portable Systems" , have shaped modern SoC design practices. With over 400 technical articles, 9 books, and an H-index of 56, his work remains highly influential.
Dr. Yiran Chen is the John Cocke Distinguished Professor at Duke University's Department of Electrical and Computer Engineering, leading the NSF AI Institute for Edge Computing (Athena) and the Duke Center for Computational Evolutionary Intelligence (DCEI). A global leader in neuromorphic computing, emerging memory systems, and edge AI, he holds prestigious roles including IEEE Fellow and Editor-in-Chief of IEEE Transactions on Circuits and Systems for AI. His research spans machine learning accelerators, security-hardened hardware, and co-design of EDA tools with LLMs. With over 700 publications and 96 patents, he has been awarded 15 paper awards and 17 nominations, including rare Technical Achievement Awards from IEEE societies. He advises over 60 PhD students and 4 postdocs, many of whom hold academic positions worldwide. His work bridges academia and industry, contributing to startups and venture capital through his board roles. Education: B.S. (Tsinghua, 1998) → M.S. (Tsinghua, 2001) → Ph.D. (Purdue, 2005). Career path: Assistant/Associate Professor at University of Pittsburgh (2010–2014) → Duke since 2014. Awards include the ACM SIGDA Outstanding New Faculty Award (2014), NSF CAREER Award (2013), and the Stansell Family Distinguished Research Award (2022). Research focuses on innovations in: (1) Non-volatile memory architectures for AI acceleration, (2) Hardware-software co-design for edge computing, (3) Security in neuromorphic systems, and (4) Large-scale ML for EDA. His group pioneered ReRAM-based accelerators like ReBNN and MARC, and introduced novel edge AI frameworks like Ecco and Prosperity. These works address scalability, energy efficiency, and real-time performance challenges. Key initiatives include the NSF IUCRC for Alternative Sustainable & Intelligent Computing (ASIC), advancing sustainable computing through novel materials and architectures. His leadership in standard-setting bodies like the IEEE Circuits and Systems Society ensures cutting-edge research translates into industry practices. Grants: Lead PIs for multiple NSF AI Institutes and industry partnerships. Labs: Directs the Athena Institute and DCEI, fostering collaboration between academia and industry. Current projects include quantum computing placement algorithms (QPlacer), federated learning frameworks (FedGPT), and neuro-symbolic architectures.
Rikky Muller is an Associate Professor of Electrical Engineering and Computer Sciences at UC Berkeley, holding the S. Shankar Sastry Professorship in Emerging Technologies. She is Co-director of the Berkeley Wireless Research Center (BWRC), a Core Member of the Center for Neural Engineering and Prostheses (CNEP), and an Investigator at the Chan-Zuckerberg Biohub. Her research focuses on implantable/wearable medical devices, low-power wireless systems, and neurotechnology for neurological applications. Education: PhD (2013), UC Berkeley; BS and M.Eng. (2004), MIT, all in EECS. Prior roles include IC designer at Analog Devices and co-founder of Cortera Neurotechnologies (acquired). Research interests include neural interfaces, closed-loop neuromodulation, and biomedical microelectronics. Notable contributions include Neural Dust (ultrasonic implants), wireless EEG systems, and seizure prediction hardware. Awards: MIT TR35 Innovator, NAE Gilbreth Lectureship, NSF CAREER Award, IEEE SSCS New Frontier Award Grants: Bakar Fellows, Hellman Fellowship, NSF CAREER Labs: Muller Lab (UC Berkeley EECS), Chan-Zuckerberg Biohub collaborations
Swiss Federal Institute of Technology in LausanneSwitzerland
Andrea Costamagna is a researcher affiliated with the École Polytechnique Fédérale de Lausanne (EPFL), working within the School of Computer and Communication Sciences and the Department of Communication Systems. His research focuses on logic synthesis, digital circuit design, and the intersection of machine learning with hardware implementation. His work includes optimizing digital circuits using techniques like resynthesis, resubstitution, and decomposition, with applications in FPGA design and low-power systems. Recent publications explore symmetry-based synthesis, glitch-aware power minimization, and the use of resistive switching devices in machine learning hardware. His research also extends to quantum physics modeling with deep learning.
Weiwen Jiang is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at George Mason University (GMU), affiliated with the College of Engineering and Computing (CEC). He leads the JQub lab, focusing on hardware/software co-design for computing systems, spanning classical (FPGAs, ASICs) and quantum computing applications in AI-driven fields like medical imaging and geophysics. Prior to GMU, he held a postdoctoral position at the University of Notre Dame and earned his PhD in Computer Science from Chongqing University with a joint PhD in Electrical and Computer Engineering from the University of Pittsburgh. His research emphasizes quantum computing, AI accelerators, and domain-specific computing. Notable achievements include the 2025 NSF CAREER Award, ACM Sigda Meritorious Service Award (2024), and IEEE QuantumWeek Best Paper Award (2023). His work is funded by NSF, DoE, ARO, Meta, and Leidos. He co-chaired IEEE QuantumWeek (2023–2025) and created workshops like StableQ at ESWEEK 2023. Key contributions include developing frameworks like QuPAD for quantum learning and JQub's AI-driven geophysical and medical imaging tools. His lab graduated Dr. Yi Sheng (now at University of South Florida) and Dr. Zhepeng Wang (Amazon Applied Scientist). Current research explores quantum machine learning, noise mitigation, and fairness in AI for edge devices.
Vidya A. Chhabria is an Assistant Professor at Arizona State University's School of Electrical, Computer and Energy Engineering. She holds a Ph.D. and M.Sc. in Electrical and Computer Engineering from the University of Minnesota (2022, 2018) and a B.E. in Electronics and Communication Engineering from M.S. Ramaiah Institute of Technology (2016). Education Ph.D. Electrical and Computer Engineering, University of Minnesota (2022) M.S. Electrical Engineering, University of Minnesota (2018) B.E. Electronics and Communication Engineering, M.S. Ramaiah Institute of Technology (2016) Her research focuses on computer-aided design (CAD) for VLSI systems, particularly addressing physical design challenges through optimization and analysis algorithms. She also explores intersections between machine learning (ML) and electronic design automation (EDA), with emphasis on sustainable computing solutions. Scientific recognition includes the ICCAD Best Paper Award (2021), the University of Minnesota Graduate School's Best Dissertation Award (2024), and a Doctoral Dissertation Fellowship (2021). She mentors students through honors directed study, thesis supervision, and doctoral research courses (EEE 525 VLSI Design, EEE 598 Special Topics). Scientific Awards ICCAD Best Paper Award (2021) University of Minnesota Graduate School Best Dissertation Award (2024) Doctoral Dissertation Fellowship (2021) Her industry experience includes internships at Qualcomm (2017) and NVIDIA Research's ASIC VLSI Research Group (2020-2021). She maintains active research through the VLSI Design and Automation (VDA) Lab at ASU.
Thuy T. Le is a Professor of Electrical Engineering at San Jose State University's College of Engineering. With a distinguished career spanning several decades, he teaches graduate and undergraduate courses in digital system design, computer architecture, microprocessor systems, and related fields. His academic journey began with earning B.S., M.S., and Ph.D. degrees from the University of California, Berkeley. Professor Le's research interests encompass a broad spectrum of cutting-edge technological domains. His primary focus areas include System-on-Chip (SoC) and Embedded System Design, Hardware Accelerators for complex algorithms, Quantum Computing, implementation of Probability theory and Monte Carlo simulation, and radiation effects on electronic devices and systems. His work bridges traditional electrical engineering with emerging computational paradigms, demonstrating a consistent ability to adapt to evolving technological landscapes while maintaining strong foundations in core engineering principles. Analysis of Professor Le's publication record reveals a consistent trajectory from nuclear reactor physics and computational methods toward modern hardware acceleration and quantum computing. His early work focused on nuclear reactor simulation and radiation shielding, then evolved to parallel computing and distributed systems, and has recently centered on hardware acceleration for complex algorithms, quantum computing applications, and AI hardware. This progression demonstrates his ability to transition between major technological paradigms while maintaining expertise in computational methods and hardware implementation. Professor Le has demonstrated significant leadership in professional service, having served as keynote speaker, general chair, technical program chair, session chair, reviewer, and committee member for numerous international conferences. His service extends beyond academia through his role as Co-Founder and Advisor of the Vietnamese Strategic Ventures Network and Chairman of the Board of the United States–Vietnam Foundation. In his educational role, Professor Le has made substantial contributions to engineering curriculum development and assessment. He has taught a wide range of courses including EE271 (Advanced Digital System Design), EE210, EE250, and various project/thesis courses. His research advising spans digital system design, ASIC, SOC, and hardware accelerators. He has also collaborated with local companies on projects related to high-performance system architectures, parallel algorithms, digital arithmetic, and System-on-Chip verification.
Professor Ahmet Bindal is a faculty member in the Department of Computer Engineering at San José State University . He earned his B.S. in Electrical Engineering from Bogazici University, Turkey, followed by M.S. and Ph.D. degrees from the University of California, Los Angeles. Industry Experience : 20 years at IBM, Intel, Philips, and Cadence Design Systems. Current Research : Nano-scale electron devices, silicon nanowire transistors, robotics, and VLSI architecture. Research Trends : His work focuses on silicon nanowire transistors for VLSI, FPGA, and robotics. Key themes include low-power/high-speed integrated circuits , dynamic logic design , neuromorphic engineering , and advanced semiconductor processing . Patents and Publications : He holds four U.S. patents (three with IBM, one with Intel). His 30+ journal and conference publications span nanowire transistors, FPGA architecture, robotics, and semiconductor process modeling. Teaching Contributions : Developed an undergraduate System-on-Chip (SoC) course and a MOSFET design laboratory at SJSU. Books Authored : Fundamentals of Computer Architecture and Design (Springer, 2017). Electronics for Embedded Systems (Springer, 2017). Silicon Nanowire Transistors (Springer, 2017).
