Xavier Aragones Cervera

Xavier Aragones Cervera is an Associate Professor at the Polytechnic University of Catalonia (UPC), affiliated with the Department of Electronic Engineering (Departament d'Enginyeria Electrònica) within the School of Telecommunications Engineering of Barcelona (Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona). His research focuses on high-performance integrated circuits and systems design, particularly addressing substrate noise, RF circuit design, and aging effects in CMOS technologies. He leads the HIPICS (High Performance Integrated Circuits and Systems Design Group) and contributes to the EFRICS (Efficient and Robust Integrated Circuits and Systems) research group.

Education: M.S. in Telecommunication Engineering from UPC (1993), Ph.D. in Electronic Engineering from UPC (1997). His work spans over 130 publications, including peer-reviewed articles, conference presentations, and patents. Key research areas include substrate noise analysis, RFIC design, mixed-signal systems, and reliability engineering. He has advised students such as Marc Manel Molina and Juan Felipe Osorio. Collaborations include projects funded by national and European programs, focusing on microelectronics, IoT, and next-generation semiconductor technologies.

Publications highlight experimental studies on substrate noise in VCOs/PLLs, aging compensation in amplifiers, and low-power IoT designs. He has contributed to major initiatives like the Cherenkov Telescope Array and RISC-V processor development in advanced FDSOI technology. His work emphasizes bridging theoretical models with practical circuit implementations, addressing emerging challenges in nanoscale CMOS and BEYOND-CMOS technologies.