Warren Gross

Warren Gross is a Professor and Chair of the Department of Electrical & Computer Engineering at McGill University's Faculty of Engineering. Holding the prestigious James McGill Professor title, he leads research in integrated hardware systems from his office in Montreal's McConnell Engineering Building. His work bridges theoretical coding theory with practical VLSI implementations for next-generation communication networks.

Professor Gross specializes in Integrated Circuits and Systems with deep expertise in error-correcting codes, particularly polar and Reed-Muller codes. His research spans hardware acceleration for machine learning, stochastic computing architectures, and VLSI design for low-latency wireless systems. Current projects focus on 6G air interface technologies, energy-efficient edge AI, and novel decoding algorithms that balance performance with hardware constraints. The ISIP Lab (Integrated Systems and Image Processing) serves as his primary research hub, advancing both theoretical frameworks and physical implementations.

Analysis of his 2023-2025 publications reveals three dominant trends: (1) Hardware-optimized decoding algorithms for polar codes targeting sub-1ms latency in 6G systems; (2) Model compression techniques for transformer networks deployed on resource-constrained edge devices; (3) Stochastic computing approaches for combinatorial optimization problems. These themes reflect his dual focus on communication theory and efficient hardware realization, with increasing emphasis on machine learning integration.

Scientific recognition includes:

• James McGill Professor (McGill University's highest academic honor)

As Department Chair and research leader, Professor Gross oversees multiple collaborative projects with industry partners in telecommunications and semiconductor sectors. His lab maintains active partnerships with 5G/6G standardization bodies and chip manufacturers, though specific grant details aren't publicly enumerated. The ISIP Lab operates advanced VLSI design facilities and FPGA testbeds supporting both academic research and industry prototyping.

Research infrastructure includes specialized labs for stochastic computing implementation, polar code decoder validation, and edge AI acceleration. Current efforts focus on quantum-inspired annealing techniques for MIMO detection and hardware-friendly transformer architectures, with several patents pending in decoding methodology and model compression.