Rajeev Alur

Rajeev Alur is a Professor in the Department of Computer and Information Science at the University of Pennsylvania's School of Engineering and Applied Science, where he leads research in formal modeling and algorithmic analysis of computer systems.

His seminal contributions include timed automata for real-time systems, hybrid automata for discrete-continuous interactions, and visibly pushdown automata for hierarchical data like XML. These models are foundational in verification theory and practice, spanning disciplines from software engineering to cyber-physical systems. His work emphasizes rigorous mathematical frameworks to ensure reliability in complex computational environments.

Research trends highlight enduring focus on automata-based verification, with applications evolving from embedded systems to modern data-processing architectures. Key subfields include temporal logic, model checking, concurrency theory, and formal semantics for programming languages.